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Memory Efficient High Speed Systolic Array Architecture Design with Multiplexed Distributed Arithmetic for 2D DTCWT Computation on FPGA

2019 Informacije midem  
Three architectures such as reduced order structure, multiplexed DA structure and zero pad structure are designed and evaluated for its performances for DTCWT computation minimizing arithmetic operations  ...  This paper presents customized Systolic Array Architecture (SAA) design of Dual Tree Complex Wavelet (DTCWT) sub band computation based on multiplexed Distributed Arithmetic Algorithm (DAA).  ...  The zero padding logic is a multiplierless and LUTless structure that requires adders and storage registers with logic zero contents.  ... 
doi:10.33180/infmidem2019.301 fatcat:4ymojsroz5eajaenjivhw25hti

Information Theoretic Approach to Complexity Reduction of FIR Filter Design

Chip-Hong Chang, Jiajia Chen, A.P. Vinod
2008 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
ACKNOWLEDGMENT The authors would like to thank Prof. A. G. Dempster for sharing with us the source codes of their algorithms.  ...  In this paper, we propose a new formulation of CSE for the design of multiplierless FIR filters. Our formulation has led to several distinctive advantages.  ...  Therefore, the CSE problem in the design of multiplierless digital filter can be recast as a problem of synthesizing a minimal vertex set MBPG by set partitioning.  ... 
doi:10.1109/tcsi.2008.920090 fatcat:s72w7ggj6jbabpvqohgnbgor2u

Contention Resolution—A New Approach to Versatile Subexpressions Sharing in Multiple Constant Multiplications

Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
2008 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
The number of logic operator (LO) and logic depth (LD) of the multiplier blocks of the FIR filters obtained by our proposed CRAH algorithm are compared with the existing algorithms as shown in Table IV  ...  of any weight and derivatives of CRA are pro-posed to trade goals of logic depth (LD) and logic complexity versus the algorithmic efficiency.  ...  Her current research interest includes digital filter design, and computer-aided design for integrated circuit designs. Chip-Hong Chang (S'92-M'98-SM'03) received the B.Eng.  ... 
doi:10.1109/tcsi.2007.913707 fatcat:g747xsdbgnf3rdf3k5iieceyyq

An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth

A.P. Vinod, Edmund Lai, Douglas L. Maskell, P.K. Meher
2010 Integration  
logic operators and logic depth (contention resolution algorithm, CRA-2 [F.  ...  Jong, Contention resolution algorithm for common subexpression elimination in digital filter design, IEEE Trans. Circuit Syst. II 52(10) (2005) 695-700 (October)]) is 15%.  ...  In [5] , a nonrecursive signed CSE (NR-SCSE) algorithm has been proposed as a modification of the technique in [3] that minimizes the logic depth into the digital structure.  ... 
doi:10.1016/j.vlsi.2009.07.001 fatcat:qllbsotkb5expf3x6tckudgoru

An Improved Non-CSD 2-Bit Recursive Common Subexpression Elimination Method to Implement FIR Filter

Hassan Kamal
2011 ETRI Journal  
An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared  ...  The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression  ...  , and the number of adder steps will dictate the logic depths (LDs).  ... 
doi:10.4218/etrij.11.0110.0642 fatcat:otmrayjnzzbk3d62dfnvx6kgu4

The M2DC Project: Modular Microserver DataCentre

Mariano Cecowski, Giovanni Agosta, Ariel Oleksiak, Michal Kierzynka, Micha vor dem Berge, Wolfgang Christmann, Stefan Krupop, Mario Porrmann, Jens Hagemeyer, Rene Griessl, Meysam Peykanu, Lennart Tigges (+13 others)
2016 2016 Euromicro Conference on Digital System Design (DSD)  
This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs.  ...  The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware.  ...  Emphasizing the capabilities of high-level synthesis tools in order to implement new designs or migrate software tasks onto FPGAs, the survey of [6] gives an in-depth overview of the different tools  ... 
doi:10.1109/dsd.2016.76 dblp:conf/dsd/CecowskiAOKBCKP16 fatcat:bu4nbkqaejebjafrotibui6mkq

2021 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 68

2021 IEEE Transactions on Circuits and Systems - II - Express Briefs  
The Author Index contains the primary entry for each item, listed under the first author's name.  ...  The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination.  ...  Zhang, Y., +, TCSII Dec. 2021 3532-3536 Design of a New Dual-Band Balanced-to-Balanced Filtering Power Divider Based on the Circular Microstrip Patch Resonator.  ... 
doi:10.1109/tcsii.2022.3144928 fatcat:bm53w7gva5bthholfhhiq4yg3a

Design and Analysis of Johnson Counter Using Finfet Technology

Myneni Jahnavi Myneni Jahnavi
2013 IOSR Journal of VLSI and Signal processing  
In this paper, we proposes a synchronous johnson counter by using FinFET Technology.FinFET logic implementation has significant advantages over static CMOS logic in terms of power consumption.  ...  Usually, the second gate of FinFET transistors is used to dynamically control the threshold voltage of the first gate in order to improve the performance and reduce leakage power.  ...  Siva Yellampalli of UTL technologies for their support in the lab, and especially the first author is thankful to the management of Don Bosco Institute of Technology, Bangalore for their constant encouragement  ... 
doi:10.9790/4200-0160106 fatcat:hdbvjkcldbhutardkebeuqei5y

A new binary arithmetic for finite-word-length linear controllers: MEMS applications

A. K. Oudjida, A. Liacha, M. L. Berrandjia, N. Chaillet
2014 2014 9th International Design and Test Symposium (IDT)  
Algorithm, an existing algorithm for signed multiplication CAD Computer-aided design, tools for design automation CDE Common Digit Elimination CLB Configurable Logic Bloc CMOS Complementary Metal Oxide  ...  The radix-2 r arithmetic was applied to the hardware integration of two FWL structures: a linear time variant PID controller and a linear time invariant LQG controller with a Kalman filter.  ...  Thus, a total of 5 additions is needed. The number of additions can be minimized using for instance the exhaustive algorithm MAG [47].  ... 
doi:10.1109/idt.2014.7038608 dblp:conf/idt/OudjidaLBC14 fatcat:ykr7hhrd7ndy5jbmu53hb3t7vm

A Low-Power Hardware Accelerator for ORB Feature Extraction in Self-Driving Cars

Raul Taranco, Jose-Maria Arnau, Antonio Gonzalez
2021 2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)  
We propose a genetic algorithm to generate an optimal memory access pattern offline, which greatly simplifies the hardware while minimizing bank conflicts in the computation of the BRIEF descriptor.  ...  ORB-SLAM is a state-of-the-art Visual SLAM system based on cameras that can be used for self-driving cars.  ...  based on a genetic algorithm that minimizes the number of conflicts in the banks for any rotation angle.  ... 
doi:10.1109/sbac-pad53543.2021.00013 fatcat:smmrjbul7vc4dg4wgtrwnqeiqa

Technical Program

2022 2022 IEEE International Conference on Consumer Electronics (ICCE)  
The paper proposes a high dynamic range (HDR) tone mastering system which dynamically corrects the picture quality based on creative intent metadata to preserve content providers' creative intent in different  ...  Multiple sections of tone mapping curves with multiple adjustment points along explicit Bezier curve is modified for better tone mapping curve control.  ...  The new algorithm is designed to be well-deployed onto such complex systems, and follow the fundamental goal -minimizing energy, not simply reducing the power.  ... 
doi:10.1109/icce53296.2022.9730380 fatcat:csqu3xqbczgdhpp3hbmvjpt26a

High Bit-Depth Seismic Data Compression: A Novel Codec Under the Framework of HEVC

Milos Radosavljevic, Zixiang Xiong, Ligang Lu, Detlef Hohl, Dejan Vukobratovic
2020 IEEE Access  
to the new data statistics, core transform and quantization have been reimplemented to handle the increased bit-depth range, and modified adaptive binary arithmetic coder has been employed for efficient  ...  To this end, we modify almost all components of the original HEVC codec to cater for high bit-depth coding of seismic data: Lagrange multiplier used in optimization of the coding parameters has been adapted  ...  Thus, we have designed the new, custom tailored, codec for high bit-depth data under the framework of HEVC and reported very good results using it for the compression of 32 b/p seismic data.  ... 
doi:10.1109/access.2020.3003682 fatcat:wfnlzgd77fhgdpylfrtepd73mi

Survey of FPGA applications in the period 2000 – 2015

Johannes Romoth, Mario Porrmann, Ulrich Rückert
2017
This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs.  ...  The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware.  ...  Emphasizing the capabilities of high-level synthesis tools in order to implement new designs or migrate software tasks onto FPGAs, the survey of [6] gives an in-depth overview of the different tools  ... 
doi:10.13140/rg.2.2.16364.56960 fatcat:dpus7ladkvcbpe7x5htvlzrt3u

An Efficient Reduction of Are In MultistandardTransform Core Sharing Using Common Sharing Distributed Arithmetic

M Deepika, M Ravikumar
unpublished
Common sharing distributed arithmetic(CSDA) combines factor sharing and distributed arithmetic sharingtechniques, efficiently reducing the number of adders for highhardware-sharing capability.  ...  Measurements show that the proposed CSDAMSTcore achieves a high-throughput rate of 1.28 G-pels/s,supporting the (4928×2048@24 Hz) digital cinema or ultrahighresolution format.  ...  Lim, are proposed A popular technique in the design of multiplierless FIR filters explores the common subexpression sharing when the filter coefficients are optimized.  ... 
fatcat:7gptieeidzcwhnyz7qfckddax4

Real-time Digital Signal Processing for Software-defined Optical Transmitters and Receivers

Rene Marcel Schmogrow
2014
Thereby, the quantization depth is determined by the number of resolution bits of the digitizer (e.g. an ADC).  ...  The process of synthesis (or logic synthesis) translates the RTL description into so-called netlists that contain the design implementation in terms of logic gates.  ...  the average power   In real life, oversampling the base functions by a factor q (preferably q = 2) is needed to simplify the filtering of a Nyquist channel.  ... 
doi:10.5445/ksp/1000042847 fatcat:juzwyq5mazhxtlan73n756h4lq
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