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Transient Fault Tolerant QDI Interconnects Using Redundant Check Code

Guangda Zhang, Wei Song, Jim D. Garside, Javier Navaridas, Zhiying Wang
2013 2013 Euromicro Conference on Digital System Design  
This paper presents a novel scheme to improve the robustness of asynchronous systems. Our first contribution is a fault tolerant delay-insensitive redundant check coding scheme named DIRC.  ...  Using DIRC in 4-phase 1-of-n quasi-delay-insensitive (QDI) interconnects, all 1-bit and some multi-bit transient faults can be tolerated.  ...  This paper proposes a novel transient fault tolerant coding scheme for 4-phase 1-of-n QDI interconnects.  ... 
doi:10.1109/dsd.2013.11 dblp:conf/dsd/Zhang0GNW13 fatcat:5wonqcwozjhfvnsk5m3vbendem

Fault Tolerant Delay Insensitive Inter-chip Communication

Yebin Shi, Steve B. Furber, Jim Garside, Luis A. Plana
2009 2009 15th IEEE Symposium on Asynchronous Circuits and Systems  
Various methods have been tested for reducing or eliminating deadlock, including a novel phase-insensitive 2-phase to 4-phase converter, a priority arbiter for reliable code conversion and a scheme that  ...  In the SpiNNaker system -a massively parallel computation platform -a DI system-wide communication infrastructure is employedwhich uses a 4-phase 3-of-6 code for on-chip communication and a 2-phase 2-of  ...  By analyzing the reasons for deadlock and comparing different 2-phase to 4-phase conversion circuits, fault tolerant implementations of the inter-chip interfaces were devised.  ... 
doi:10.1109/async.2009.21 dblp:conf/async/ShiFGP09 fatcat:6uwxlapm35b73mckb42ftczgsm

Asynchronous transient resilient links for NoC

Simon Ogg, Bashir Al-Hashimi, Alex Yakovlev
2008 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis - CODES/ISSS '08  
We demonstrate it is possible to achieve a similar number of transitions per bit as existing delay insensitive codes, from a power consumption point of view, but achieving resilience to transient faults  ...  This paper proposes a new link for asynchronous NoC communications that is resilient to transient faults on the wires of the link without impact on the data transfer capability.  ...  Acknowledgements The authors would like to acknowledge the Engineering and Physical Sciences Research Council (EPSRC) for funding under grant no. EP/C512804 and EP/C512812.  ... 
doi:10.1145/1450135.1450182 dblp:conf/codes/OggAY08 fatcat:igqqykj7sfgfdcyyqlfgczogkq

TITAC: design of a quasi-delay-insensitive microprocessor

T. Nanya, Y. Ueno, H. Kagotani, M. Kuwako, A. Takamura
1994 IEEE Design & Test of Computers  
Acknowledgments We thank Masahide Takada and Osamu Fujita of Microelectronics Research Lab, NEC Corporation, for their cooperative work in the fabrication of TITAC.  ...  Two-phase, event-driven scheme We based the TITAC design on a t w o phase, event-driven scheme.  ...  Without a global clock, asyn- design flexibility and cost reduction, with higher level logic design separated from lower level timing design timing fault tolerance, thanks to insensitivity to delay variance  ... 
doi:10.1109/54.282445 fatcat:xhil6kqdonhthbdz7phps2ohmy

On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip

Wei Song, Guangda Zhang, Jim Garside
2014 Proceedings of the 24th edition of the great lakes symposium on VLSI - GLSVLSI '14  
Similar to synchronous NoCs, asynchronous NoCs are vulnerable to faults but their fault-tolerance is not studied adequately, especially the quasi-delay insensitive (QDI) NoCs.  ...  One of the key issues neglected by most designers is that permanent faults in QDI NoCs cause deadlocks, which cripples the traditional fault-tolerant techniques using redundant codes.  ...  RELATED WORK Fault-tolerance is a well-studied topic in synchronous NoCs. Transient faults can be dynamically detected using redundant coding schemes.  ... 
doi:10.1145/2591513.2591518 dblp:conf/glvlsi/0002ZG14 fatcat:zxskkpdwevferc57uhnx25hzhq

Implementation of error correcting methods to the asynchronous Delay Insensitive codes with reduced delay and area

Shilpa Reddy
2013 IOSR Journal of Electronics and Communication Engineering  
A new class of error correcting Delay Insensitive (ie., unordered) codes is introduced for global asynchronous communication.It simultaneously provides timing-robustness and fault tolerance for the codes.A  ...  This Paper provides an approach for reducing delay and area in asynchronous communication.  ...  Data is encoded in a unified field, which ensures delay insensitivity. Dual-rail, 1-of-4 and general class of m-of-n codes are example for these codes. .  ... 
doi:10.9790/2834-0757885 fatcat:454jgabbkrenrhpvaxxh3gqf34

Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis

Matheus Trevisan Moreira, Ricardo Aquino Guazzelli, Guilherme Heck, Ney Laert Vilar Calazans
2014 Proceedings of the 24th edition of the great lakes symposium on VLSI - GLSVLSI '14  
The latter is a logic style based on the return-to-one 4-phase protocol.  ...  It accordingly proposes the alternative use of the delay-insensitive maxterm synthesis for hardening QDI circuits against transient faults.  ...  However, according to Martin and Nyström in [1] , the majority of current asynchronous circuits rely on the quasidelay-insensitive (QDI) delay model, using 4-phase handshaking coupled to 1-of-n delay-insensitive  ... 
doi:10.1145/2591513.2591531 dblp:conf/glvlsi/MoreiraGHC14 fatcat:upl5s4vq4nflpie6evrlo2umc4

Fault-Tolerant Techniques to Minimize the Impact of Crosstalk on Phase Encoded Communication Channels

Basel Halak, Alex Yakovlev
2008 IEEE transactions on computers  
Three fault tolerant schemes are introduced which are based on information redundancy techniques and the partial order coding concept.  ...  It is shown that a substantial improvement in the performance can be obtained for four wire channels when using the fault tolerant design approach, at the cost of 25% of information capacity per symbol  ...  Fault Tolerance Techniques In this section three fault tolerance techniques for phase encoding transmission protocol will be introduced.  ... 
doi:10.1109/tc.2007.70825 fatcat:5mivn26rqfbybjhcjsbmnzykqm

Efficient Channel Coding Scheme for Optical Memory: An Overview

Jesna Jose
2019 International Journal for Research in Applied Science and Engineering Technology  
Here encoding scheme is preferred that is Low-Density Parity-Check coding, which is a class of linear block codes and also an error correcting code.  ...  LDPC codes are the most powerful error correcting codes. And this encoding scheme is compared with another encoding scheme and get the most hardware efficient encoding scheme.  ...  Wei Hu, Diqing Hu, Changsheng Xie and Fan Chen [4] proposes a new scheme for the optical storage system.  ... 
doi:10.22214/ijraset.2019.4021 fatcat:b3duvylhnfcyjnhj56iosq2cfe

Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation

Marcus Jeitler, Jakob Lech
2009 2009 International Conference on Reconfigurable Computing and FPGAs  
Using a soft-core processor as an example, this paper shows how an off-the-shelf FPGA can be used for asynchronous Four State Logic designs, on which future fault injection experiments will be conducted  ...  While stability and robustness of synchronous circuits becomes increasingly problematic due to shrinking feature sizes, delay-insensitive asynchronous circuits are supposed to provide inherent protection  ...  Figure 1 illustrates the LEDR coding scheme and shows the corresponding transition diagram. Even phases are denoted with ϕ 0 , odd phases with ϕ 1 .  ... 
doi:10.1109/reconfig.2009.35 dblp:conf/reconfig/JeitlerL09 fatcat:cucl3aylgnemzgm22cfrxsyydy

Robust event correlation scheme for fault identification in communication networks

Chi-Chun Lo, Shing-Hong Chen
1999 International Journal of Communication Systems  
This paper proposes a novel event correlation scheme for fault identi"cation in communication networks. This scheme is based on the algebraic operations of sets.  ...  From simulation results, we notice that this scheme not only identi"es multiple disorders at one time but also is insensitive to noise.  ...  For the coding scheme, which consists of the codebook selection phase and the decoding phase, its time complexity can be shown to be equal to n k ;M"O(M ) nI) (11) where n represents the number of observed  ... 
doi:10.1002/(sici)1099-1131(199905/06)12:3<217::aid-dac397>3.0.co;2-b fatcat:uqhri4tfvfc3tjro2hu2w6jcv4

Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications [article]

P Balasubramanian, D L Maskell, N E Mastorakis
2020 arXiv   pre-print
The delay insensitive dual rail code was used for data encoding, and 4-phase return-to-zero and return-to-one handshake protocols were used for data communication.  ...  Recently, quasi delay insensitive (QDI) asynchronous majority voters for TMR applications were also discussed in the literature.  ...  The inputs and outputs of a QDI circuit are encoded using a delay insensitive code [23] . Among the family of delay insensitive codes, the dual rail code is widely used for QDI circuit designs.  ... 
arXiv:2008.05685v1 fatcat:26amuxdgjzdgvbtapperauv43y

Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic

Jurgen Maier, Andreas Steininger
2014 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems  
Complementing concurrent checking with online testing is crucial for preventing fault accumulation in fault-tolerant systems with long mission times.  ...  The key idea is to use the protocol's unproductive NULL phase for processing test vectors, thus effectively interleaving the incoming 4-phase data stream with a test data stream in a 2-phase fashion.  ...  In contrast, the delay insensitive 1 approach uses a more elaborate coding for the data that allows the receiver to evaluate, by means of a so-called completion detector, when a received data item is valid  ... 
doi:10.1109/ddecs.2014.6868759 dblp:conf/ddecs/MaierS14 fatcat:xm3uaokowjet3daddg7fel74q4

Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy

Jan Belohoubek, Petr Fiser, Jan Schmidt
2015 2015 Euromicro Conference on Digital System Design  
In this work we present a novel fault-tolerant circuits design method.  ...  The offline-testable module with an online-checker allows to compose a fault-tolerant system with the mentioned properties. This system will be denoted as a time-extended duplex scheme.  ...  Quasi-delay insensitive (QDI) [8] is a class of asynchronous circuits using dual-rail logic for value propagation and completion detection.  ... 
doi:10.1109/dsd.2015.95 dblp:conf/dsd/BelohoubekFS15 fatcat:hoyg2ij2kzbfheoevvf5xts6oy

Building a large-scale quantum computer with continuous-variable optical technologies [article]

Kosuke Fukui, Shuntaro Takeda
2021 arXiv   pre-print
Realizing a large-scale quantum computer requires hardware platforms that can simultaneously achieve universality, scalability, and fault tolerance.  ...  In particular, we focus on scaling-up technologies enabled by time multiplexing, bandwidth broadening, and integrated optics, as well as hardware-efficient and robust bosonic quantum error correction schemes  ...  For example, transmitting a 1-km optical fiber introduces 5% loss, which is below the fault-tolerant threshold for some QEC schemes [103] .  ... 
arXiv:2110.03247v1 fatcat:jkh4xnziifftjipkj3pympbwba
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