A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf
.
Filters
An In-Field Programmable Adaptive CMOS LNA for Intelligent IOT Sensor Node Applications
[article]
2019
arXiv
pre-print
This paper develops reconfiguration approaches that enable post-production adaptation of circuit performance to enable RF IC re-use across different IOT applications. ...
A statistical model that relates circuit-level reconfiguration parameters to circuit performances is generated by characterizing a limited number of samples. ...
DUT and is used as the input to the statistical model for For better understanding of the neural network algorithm a
prediction results. ...
arXiv:1904.12999v1
fatcat:rem5jsronfgifooionnuekrwaa
Post-silicon Receiver Equalization Metamodeling by Artificial Neural Networks
2018
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
In this paper, a metamodeling approach based on neural networks is proposed to efficiently simulate the effects of a receiver equalizer PHY tuning settings. ...
Current industrial practices for PHY tuning in HSIO links are very time consuming since they require massive lab measurements. ...
This neural model can be later used for efficient circuit tuning at post-silicon validation. ...
doi:10.1109/tcad.2018.2834403
fatcat:l2ojb3dcrjecbexu525cx2vstm
Digital-to-analog and analog-to-digital conversion with metal oxide memristors for ultra-low power computing
2013
2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
In particular, a binary-weighted implementation is demonstrated for DAC, while ADC is implemented with a Hopfield neural network circuit. ...
The paper presents experimental demonstration of 6-bit digital-to-analog (DAC) and 4-bit analog-to-digital conversion (ADC) operations implemented with a hybrid circuit consisting of Pt/TiO 2-x /Pt resistive ...
In this paper, we demonstrate binary-weighted DAC and Hopfield-network ADC circuits which utilize the feature of post-fabrication resistance tuning for achieving energy-efficient conversion. ...
doi:10.1109/nanoarch.2013.6623031
dblp:conf/nanoarch/GaoMAGHCS13
fatcat:rpq7eqooabdelcsmscdy4yw4zm
Implementation of multilayer perceptron network with highly uniform passive memristive crossbar circuits
2018
Nature Communications
The demonstrated network, whose hardware complexity is almost 10× higher as compared to previously reported functional classifier circuits based on passive memristive crossbars, achieves classification ...
Recent works have shown that mixed-signal integrated memristive circuits, especially their passive (0T1R) variety, may increase the neuromorphic network performance dramatically, leaving far behind their ...
For example, the crude estimates showed that energy-delay product for the inference operation of a large-scale deep learning neural networks implemented with mixed-signal circuits based on the 200-nm memristor ...
doi:10.1038/s41467-018-04482-4
pmid:29899421
pmcid:PMC5998062
fatcat:snr4m6sdmbfazgqwfyjx2h4goi
Implementation of Multilayer Perceptron Network with Highly Uniform Passive Memristive Crossbar Circuits
[article]
2017
arXiv
pre-print
The demonstrated multilayer perceptron network, whose complexity is almost 10x higher as compared to previously reported functional neuromorphic classifiers based on passive memristive circuits, achieves ...
Recent works have shown that mixed-signal integrated memristive circuits, especially their passive ('0T1R') variety, may increase the neuromorphic network performance dramatically, leaving far behind their ...
Efficient training algorithms for neural networks based on memristive crossbar circuits. In: International Joint Conference on Neural Networks 1-8 (2015).
12. Likharev, K. K. ...
arXiv:1712.01253v1
fatcat:4l65trewenf3zcxdy6tzvgfp5y
CMOS micromachined probes by die-level fabrication for extracellular neural recording
2007
Journal of Micromechanics and Microengineering
A convenient fabrication process is proposed for making integrated recording probes at the die level, providing a low-cost solution for academic research as compared to the more expensive wafer-level approach ...
The on-chip circuit, used for recording action potential signals of neural activities, provides a stable dc bias when operating in electrolyte. ...
The circuit output noise shown in figure 9 was measured using an Agilent 4295A network/spectrum analyzer with a grounded circuit input. ...
doi:10.1088/0960-1317/17/2/014
fatcat:tfbmj6m6pja5vftwycpcsfmu6a
Mapping arbitrary mathematical functions and dynamical systems to neuromorphic VLSI circuits for spike-based neural computation
2014
2014 IEEE International Symposium on Circuits and Systems (ISCAS)
The Neural Engineering Framework provides a method for programming these devices to implement computation. ...
This is achieved by means of a network of spiking neurons with multiple weighted connections. The synaptic weights are stored in a 4-bit on-chip programmable SRAM block. ...
One promising approach is that of implementing brain-inspired models of neural computation, based on massively parallel networks of lowpower silicon neuron circuits [3] . ...
doi:10.1109/iscas.2014.6865117
dblp:conf/iscas/CorradiEI14
fatcat:imalaetxrrfknaufkvygnf6vcq
Neuromorphic Silicon Neurons and Large-Scale Neural Networks: Challenges and Opportunities
2011
Frontiers in Neuroscience
The intrinsic VLSI process variability severely limits the scalability of SiN networks since it is not practicable to fine-tune a large number of analog transistor circuits to correct for mismatch on chip ...
To be sure, neural modeling "in silico" as practiced today is still largely digital software-based rather than analog silicon chip-based, and for obvious reasons. ...
doi:10.3389/fnins.2011.00108
pmid:21991244
pmcid:PMC3181466
fatcat:sohj6ggjf5bsrmwitmjxycdkrq
A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons
2009
2009 International Joint Conference on Neural Networks
The output is inhibitorily fedback to the three neuronal circuits through a capacitive coupling, tuned to obtain a winners-shareall network operation. ...
The circuit performance was evaluated through Monte-Carlo based computer simulations. ...
A theoretical investigation of noise-shaping in neural networks is elaborated by Mar et. al [17] . ...
doi:10.1109/ijcnn.2009.5178715
dblp:conf/ijcnn/KikomboAOSLA09
fatcat:kjfy33yfrrgwxj2mupqsffbcdm
Analog circuits for mixed-signal neuromorphic computing architectures in 28 nm FD-SOI technology
[article]
2019
arXiv
pre-print
with the environment in real-time, and for high-frequency operation for fast data processing in different types of spiking neural network architectures. ...
We present circuit simulation results, based on a new chip that has been recently taped out, to demonstrate how the circuits can be useful for both low-frequency operation in systems that need to interact ...
neural networks. ...
arXiv:1908.07874v1
fatcat:2nnjvyxmlfdsrpua2jpofspn7a
Spintronics for neuromorphic computing
[article]
2020
arXiv
pre-print
Here we review the development of spintronic devices for neuromorphic computing. ...
Approaches that use traditional electronic devices to create artificial neurons and synapses are, however, currently limited by the energy and area requirements of these components. ...
This theoretical work shows that skyrmion fabrics are suitable for reservoir computing, providing a path to solve complex tasks using linear post-processing techniques based on nanostructures. ...
arXiv:2007.06092v1
fatcat:3m5pfeedmnhq5h7nbjw77zvdi4
Neuromorphic Electronic Systems for Reservoir Computing
[article]
2020
arXiv
pre-print
Moreover, to deal with challenges of computation on such unconventional substrates, several lines of potential solutions are presented based on advances in other computational approaches in machine learning ...
This chapter provides a comprehensive survey of the researches and motivations for hardware implementation of reservoir computing (RC) on neuromorphic electronic systems. ...
Stochastic activity-based STDP approach [42] , structural plasticity-based mechanism [43] , and correlation-based neuron gating rule [44] have also been introduced for efficient low-resolution tuning ...
arXiv:1908.09572v2
fatcat:cimkbnvyrjc3lhixlyufgmqy3i
A Survey on Silicon Photonics for Deep Learning
[article]
2021
arXiv
pre-print
execute the deep neural network models. ...
Many application-specific integrated circuit (ASIC) hardware accelerators for deep learning have garnered interest in recent years due to their improved performance and energy-efficiency over conventional ...
Devices based on Phase-change Materials Devices that utilize phase-change materials (PCM) for tuning are of great interest in silicon photonic circuits to design modulators [115] , MZI-based switches ...
arXiv:2101.01751v2
fatcat:jorj4q6tjjewxfkbbovnxvpdyi
Spintronic nano-devices for bio-inspired computing
[article]
2016
arXiv
pre-print
However, one of the major challenges of fabricating bio-inspired hardware is building ultra-high density networks out of complex processing units interlinked by tunable connections. ...
Large networks of interacting spintronic nano-devices can have their interactions tuned to induce complex dynamics such as synchronization, chaos, soliton diffusion, phase transitions, criticality, and ...
This is necessary for a neural network to accomplish hard tasks such [82] . ...
arXiv:1606.07700v2
fatcat:h5eorqvne5d4hc4gvyj2pystlm
Recent advances, perspectives and challenges in ferroelectric synapses
[article]
2020
arXiv
pre-print
efficient neural network. ...
Ferroelectric synapses are potential for the construction of low-energy and effective brain-like intelligent networks. ...
These results demonstrate a high potential of HZO-based FTJs to form complex hardware neural network applications. ...
arXiv:2007.06914v1
fatcat:n4mcxwvmhbhtdjoiatdjnkvqvm
« Previous
Showing results 1 — 15 out of 3,519 results