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Duo Ding, David Z. Pan
2009 Proceedings of the 11th international workshop on System level interconnect prediction - SLIP '09  
In this paper, we present OIL, a parameterized Optical Interconnect Library of silicon nano-photonic devices for system level interconnect planning/analysis and low power high performance design exploration  ...  under a new holistic photonic Networks-on-Chip architecture.  ...  Under photonic networks-on-chip architecture, a modulator is to be inserted at each gateway (G) on every processing unit of a chip multi-processor.  ... 
doi:10.1145/1572471.1572475 dblp:conf/slip/DingP09 fatcat:qcayeyu3cnevfliwmbcfgnqhuy

Front Matter: Volume 9753

2016 Optical Interconnects XVI  
A unique citation identifier (CID) number is assigned to each article at the time of publication.  ...  using a Base 36 numbering system employing both numerals and letters.  ...  9753-5] SESSION 2 NANOPHOTONICS FOR OPTICAL INTERCONNECTS 9753 07 A chip scale optical Tx/Rx based on silicon photonics from views of multi-mode transmission (Invited Paper) [9753-6] 9753 08  ... 
doi:10.1117/12.2240147 fatcat:mj2vdgduq5bcraeki7t3syjhmi

Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for Multicores

Randy Wayne Morris Jr., Avinash Karanth Kodi
2010 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip  
Network-on-Chips (NoCs) are becoming the defacto standard for interconnecting the increasing number of cores in chip multiprocessors (CMPs) by overcoming the scalability and wire delay problems of shared  ...  In this paper, we propose ET-PROPEL (Extended Token based Photonic Reconfigurable On-Chip Power and Area-Efficient Links) architecture to utilize the emerging nanophotonic technology to design a high-bandwidth  ...  Figure 5(a) shows the operating principle of a double micro-ring resonator allowing light of the same wavelength to be switched between the two waveguides. λ (1) 0 is switched to the bottom waveguide  ... 
doi:10.1109/nocs.2010.30 dblp:conf/nocs/MorrisK10 fatcat:rsp6xq7j45anxh2bbwkenezvau

Challenges in Integration of Microelectronics & Photonics with Nano-chemistry

Mohd. Muzaffar Ahmad, Mohd. Abdul Sattar, Mohd. Anas Ali
2017 IJARCCE  
Although silicon technology is evolving continuously to produce smaller, faster and reliable systems with low power, eventually the integration of Microelectronics and Photonics with Nano-chemistry as  ...  The co-existence of silicon technology with these emerging technologies, photonics and nano-chemistry has created new design opportunities for the designer, bringing new challenges to be solved.  ...  Micro/nano-photonic wires and devices are interconnected and integrated on a chip to form micro/nano circuits of various functions that are compact, high speed, intelligent, light weight, low energy and  ... 
doi:10.17148/ijarcce.2017.6113 fatcat:bw26pecd65buzjzjzgnmiwr6je

Survey on Unified Inter/Intrachip Optical Network for Chip Multiprocessors

Priyanka Rajendran, Dr.Gnana Sheela K
2014 IOSR Journal of VLSI and Signal processing  
As modern computing systems become increasingly complex, communication efficiency among and inside chips has become as important as the computation speeds of individual processing cores.  ...  It connects not only cores on a single CMP, but also multiple CMPs in a system.  ...  It introduces a novel hybrid micro architecture for NoCs that combines a broadband photonic circuit-switched network with an electronic overlay packet-switched control network.  ... 
doi:10.9790/4200-04615261 fatcat:ckatiqftd5db5h4ug5b2zlsbra

Design of a scalable nanophotonic interconnect for future multicores

Avinash Kodi, Randy Morris
2009 Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems - ANCS '09  
In this paper, we propose PROPEL, a balanced power and area-efficient on-chip photonic interconnect for future multicores.  ...  PROPEL overcomes two fundamental issues facing NoCs architectures, namely power dissipation and area overhead, by a combination of multiplexing techniques (wavelength and space) and by exploiting the recent  ...  The optical complexity analysis clearly showed that PROPEL is significantly cost-efficient than previously proposed on-chip photonic interconnects while delivering comparable performance at reduced power  ... 
doi:10.1145/1882486.1882516 dblp:conf/ancs/KodiM09 fatcat:sbd7peiiqzghblcylhhklrivfy

Flex-LIONS: a Silicon Photonic Bandwidth-Reconfigurable Optical Switch Fabric

Roberto Proietti, Xian Xiao, Marjan Fariborz, Pouya Fotouhi, Yu Zhang, S.J.Ben Yoo
2020 IEICE transactions on communications  
This paper summarizes our recent studies on architecture, photonic integration, system validation and networking performance analysis of a flexible low-latency interconnect optical network switch (Flex-LIONS  ...  traffic profiles (a legacy fat-tree architecture is used for comparison).  ...  (a) and (b) show the micro- Fig. 2 2 (a) Microscope image of the fabricated 8 × 8 SiPh Flex-LIONS (N = 8, b = 3) chip with multi-wavelength MRR crossbar.  ... 
doi:10.1587/transcom.2019obi0004 fatcat:7ej5zndptfbhvpne6n6tsvungu

Modeling and Evaluation of Chip-to-Chip Scale Silicon Photonic Networks

Robert Hendry, Dessislava Nikolova, Sebastien Rumley, Keren Bergman
2014 2014 IEEE 22nd Annual Symposium on High-Performance Interconnects  
Two chip-to-chip interconnection architectures. (a) A switched architecture with a separate switching chip and a central arbiter. (b) A full mesh architecture with a central arbiter.  ...  of silicon photonic chip-to-chip designs.  ...  Department of Energy Sandia National Laboratories PO 1426332.  ... 
doi:10.1109/hoti.2014.14 dblp:conf/hoti/HendryNRB14 fatcat:n3rgzx5vlzfl7ia54vvctxt7tu

Optics in Computing: From Photonic Network-on-Chip to Chip-to-Chip Interconnects and Disintegrated Architectures

Theonitsa Alexoudi, Nikolaos Terzenidis, Stelios Pitris, Miltiadis Moralis-Pegios, Pavlos Maniotis, Christos Vagionas, Charoula Mitsolidou, George Mourgias-Alexandris, George T. Kanellos, Amalia Miliou, Konstantinos Vyrsokinos, Nikos Pleros
2019 Journal of Lightwave Technology  
Postdoctoral Researchers", in the framework of the Operational Programme "Human Resources Development Program, Education and Lifelong Learning" of the National Strategic Reference Framework (NSRF) 2014  ...  Alexoudi acknowledges support from the IKY scholarships program that is co-financed by the European Union (European Social Fund -ESF) and Greek national funds through the action entitled "Reinforcement of  ...  Building on the state-of-art pNoC implementations [46] - [66] and photonics-enabled multi-socket architectures [75] - [77] , we conclude to a solid case for employing integrated photonics in inter-chip  ... 
doi:10.1109/jlt.2018.2875995 fatcat:gxlflc7gfjfqrd7f3efmoiq3uy

UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications

Shirish Bahirat, Sudeep Pasricha
2010 2010 11th International Symposium on Quality Electronic Design (ISQED)  
In this paper we propose UC-PHOTON, a novel hybrid photonic NoC communication architecture optimized to cope with the variable bandwidth and latency constraints of multiple use-case applications implemented  ...  NoC fabrics, highlighting the benefits of using the novel communication fabric.  ...  On-chip Photonic Interconnects: Overview Recently, photonic interconnects have been proposed as a solution to overcome the on-chip communication power bottleneck [13] .  ... 
doi:10.1109/isqed.2010.5450500 dblp:conf/isqed/BahiratP10 fatcat:tr6jporxebdipnrqv7m4vrrnve

Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors

Shirish Bahirat, Sudeep Pasricha
2009 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09  
In this paper, we explore using photonic interconnects on a chip to enhance traditional electrical NoCs.  ...  Increasing application complexity and improvements in process technology have today enabled chip multiprocessors (CMPs) with tens to hundreds of cores on a chip.  ...  A few other works have also explored non-blocking micro-resonator based photonic switches [4] [28] [31] for routing photonic messages.  ... 
doi:10.1145/1629435.1629453 dblp:conf/codes/BahiratP09 fatcat:w3ih26hblrbe7pipe6q7ye7itq

Exploiting New Interconnect Technologies in On-Chip Communication

John Kim, Kiyoung Choi, Gabriel Loh
2012 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
We provide an overview of the different technologies that are available and then, investigate how these interconnect technologies impact the architecture of the on-chip communication and the system design  ...  The communication challenge is not only within a single chip but providing high bandwidth to the increasing number of cores from off-chip memory is also a challenge.  ...  The additional cost of multi-hop routing using a global interconnect can also be a problem if the global interconnect is used as point-to-point channels in a multi-stage topology as the benefit can be  ... 
doi:10.1109/jetcas.2012.2201031 fatcat:3arzyh25zrcybaqc3sqlocus2q

PINE: Photonic Integrated Networked Energy efficient datacenters (ENLITENED Program)

Madeleine Glick, Nathan Abrams, Qixiang Cheng, Min Yee Teh, Yu-Han Hung, Oscar Jimenez, Songtao Liu, Yoshitomo Okawachi, Michal Lipson, Alexander Gaeta, Keren Bergman, Leif Johansson (+7 others)
2020 Journal of Optical Communications and Networking  
In phase 1 of the program, the PINE system architecture demonstrated an average factor of 2.2× improvement in transactions/joule across a diverse set of HPC and datacenter applications.  ...  The PINE program leverages the unique features of photonic technologies to enable alternative megadatacenters and high-performance computing (HPC) system architectures that deliver more substantial energy  ...  His current research interests include large networks of GPUs, switch micro-architectures, network-on-chip, and photonic interconnects.  ... 
doi:10.1364/jocn.402788 fatcat:evcrlkdyjfeunoy6fhh7aagjdy

HELIX: Design and synthesis of hybrid nanophotonic application-specific network-on-chip architectures

Shirish Bahirat, Sudeep Pasricha
2014 Fifteenth International Symposium on Quality Electronic Design  
Hybrid nanophotonic-electric networks-on-chip  ...  CMOS compatible on-chip photonic interconnects with silicon-on-insulator waveguides provide a potential substitute for electrical interconnects, particularly for global on-chip communication, allowing  ...  Network-On-Chip (NoC) architectures will play a crucial role to ensure reliable and scalable interconnects between processing cores, memory modules, cache banks, and I/O devices.  ... 
doi:10.1109/isqed.2014.6783311 dblp:conf/isqed/BahiratP14 fatcat:triuyx3lcza6feylf5s4naqbo4

Photonic Approach to Optimize Energy Consumption for On-chip Clos Network

Deepalakshmi B, Maruthachalam G
2016 Journal of Lasers Optics & Photonics  
To meet energy-efficient performance needs, the computation has positioned to parallel computer architectures, such as chip multiprocessors (CMPs), internally interconnected via networks-on-Chip (NoC)  ...  Silicon Nano photonics is a promising swap for electronic on-chip interconnect for its high data transfer capacity and low inactivity, by the by, earlier methods have required high static force for the  ...  Figure 6 : 6 Four row interconnection of PNoC of CMPs with 16 tiles. Figure 7 :Figure 8 : 78 Synthetic Power analysis.  ... 
doi:10.4172/2469-410x.1000128 fatcat:rikdqaxtzzaflkxzkefcgjhu6q
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