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A low-radix and low-diameter 3D interconnection network design

Yi Xu, Yu Du, Bo Zhao, Xiuyi Zhou, Youtao Zhang, Jun Yang
2009 2009 IEEE 15th International Symposium on High Performance Computer Architecture  
This implies long network latency due to high hop counts in network paths. In this paper, we design a low-diameter 3D network using low-radix routers.  ...  The network-on-chip (NoCs) has been proposed as a scalable and high-bandwidth fabric for interconnect design.  ...  In this paper, we develop a methodology for designing a low-diameter 3D NoC using low-radix routers to achieve low network latency.  ... 
doi:10.1109/hpca.2009.4798234 dblp:conf/hpca/XuDZZZY09 fatcat:dmvcoirugnf2hlyrhx7tmvpfwq

Highly-scalable 3D CLOS NOC for many-core CMPs

Aamir Zia, Sachhidh Kannan, Garrett Rose, H. Jonathan Chao
2010 Proceedings of the 8th IEEE International NEWCAS Conference 2010  
In this paper, we propose using 3D integrated CLOS network-on-chip (CNOC) to achieve these goals. We present the design of a 512-node 3D CNOC and evaluate its power consumption.  ...  We compare the power consumption of 3D CNOC with a planar CNOC implementation and with 2D and 3D mesh topologies.  ...  The main attraction of such low-radix topologies, when employed in small networks, is that they facilitate a simple network organization with low latency.  ... 
doi:10.1109/newcas.2010.5603776 fatcat:rbv2ofkjinav7onrwnr2ut2l2i

The Impact of Optics on HPC System Interconnects

Mike Parker, Steve Scott
2009 2009 17th IEEE Symposium on High Performance Interconnects  
new class of high-radix networks with low network diameter ⇒ lower latency ⇒ more cost-effective global bandwidth Driving down the cost of optical links will further strengthen this argument Hot Interconnects  ...  system interconnects  Cray is now designing our first hybrid electrical/optical network  Performance and price-performance of optical networks is relatively insensitive to distance  This enables a  ...   Anything that requires tuning a receiver (and thus is slow)  Optical switching (electrical switching is just fine, thanks)  Free-space optics  ... 
doi:10.1109/hoti.2009.21 dblp:conf/hoti/ParkerS09 fatcat:w4jlewdpdvhftckw5kt5qy7lcy

A Hybrid Photonic Burst-Switched Interconnection Network for Large-Scale Manycore System

Quanyou FENG, Huanzhong LI, Wenhua DOU
2012 IEICE transactions on information and systems  
We embed an electric low-diameter flattened butterfly into 3D stacking layers using integer linear programming, which results in a scalable low-latency network for inter-core packets exchange.  ...  In this paper, we propose a hybrid photonic burst-switched interconnection network for large-scale manycore processors.  ...  The new architecture provides express inter-core communication by embedding a low-diameter flattened butterfly into the 3D topology.  ... 
doi:10.1587/transinf.e95.d.2908 fatcat:rjreuzqward4ngrrnfiytzjk6e

Design Methodology for Optimizing Optical Interconnection Networks in High Performance Systems [chapter]

Sébastien Rumley, Madeleine Glick, Simon D. Hammond, Arun Rodrigues, Keren Bergman
2015 Lecture Notes in Computer Science  
With ever increasing line rates and advances in optical interconnects, there is a need for renewed design methodologies that comprehensively capture the requirements and expose trade-offs expeditiously  ...  Modern high performance computers connect hundreds of thousands of endpoints and employ thousands of switches. This allows for a great deal of freedom in the design of the network topology.  ...  Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S.  ... 
doi:10.1007/978-3-319-20119-1_32 fatcat:2ipsgym4n5dnzgvseiwzjhx6mm

Optimal Low-Latency Network Topologies for Cluster Performance Enhancement [article]

Yuefan Deng, Meng Guo, Alexandre F. Ramos, Xiaolong Huang, Zhipeng Xu, Weifeng Liu
2019 arXiv   pre-print
We propose that clusters interconnected with network topologies having minimal mean path length will increase their overall performance for a variety of applications.  ...  The optimal (or sub-optimal) low-latency network topologies are found by minimizing the mean path length of regular graphs.  ...  Hybrid 6D mesh/torus TOFU interconnect is incorporated in K computer [14] , modified 3D torus with combined 2-node is designed to form the Cray Gemini interconnect [13] , upgrading from the traditional  ... 
arXiv:1904.00513v1 fatcat:eyjwnbtdnnf5zd7oubfs2kmrgq

SpectralFly: Ramanujan Graphs as Flexible and Efficient Interconnection Networks [article]

Sinan Aksoy, Stephen Young, Jesun Firoz, Roberto Gioiosa, Mark Raugas, Juan Escobedo
2021 arXiv   pre-print
In particular, we study a novel HPC topology, SpectralFly, designed around the Ramanujan graph construction of Lubotzky, Phillips, and Sarnak (LPS).  ...  In recent years, graph theoretic considerations have become increasingly important in the design of HPC interconnection topologies.  ...  With regard to physical a long list of desirable criteria, such as low-diameter and average SpectralFly: Ramanujan Graphs as Flexible and Efficient Interconnection Networks layout, whereas for other topologies  ... 
arXiv:2104.11725v1 fatcat:jhemjrcoenbxnffnpi7srpq2le

Exploiting New Interconnect Technologies in On-Chip Communication

John Kim, Kiyoung Choi, Gabriel Loh
2012 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
In such manycore processors, the communication between cores with the on-chip interconnect is becoming a challenge as it not only must provide low latency and high bandwidth but also needs to be cost-effective  ...  We provide an overview of the different technologies that are available and then, investigate how these interconnect technologies impact the architecture of the on-chip communication and the system design  ...  As the radix increases, the network diameter decreases, which can increase performance by reducing the hop count and network latency.  ... 
doi:10.1109/jetcas.2012.2201031 fatcat:3arzyh25zrcybaqc3sqlocus2q

A New Cost Effective and Reliable Interconnection Topology for Parallel Computing Systems

2019 International Journal of Engineering and Advanced Technology  
Our results show that the proposed interconnection topology has high connectivity, lesser diameter, low cost, fault tolerant, scalable and low average distance.  ...  In this paper, we propose a new hybrid interconnection network topology called TOR-CUBE (TC) which is a product of two classical popular interconnection topologies namely hypercube and torus.  ...  The degree, diameter, and cost are the three desirable and important properties of any interconnection network, where one always needs a higher degree network with the low diameter and low cost.  ... 
doi:10.35940/ijeat.f8363.088619 fatcat:jbf7a4fp4zha3akd6r7rhw7ja4

Low Latency, High Bisection-Bandwidth Networks for Exascale Memory Systems

Shang Li, Jim Ang, Bruce Jacob, Po-Chun Huang, David Banks, Max DePalma, Ahmed Elshaarany, Scott Hemmert, Arun Rodrigues, Emily Ruppel, Yitian Wang
2016 Proceedings of the Second International Symposium on Memory Systems - MEMSYS '16  
Therefore, focusing on low latency (e.g., low diameter) networks that also have high bisection bandwidth is critical.  ...  We identify several designs that have reasonable port costs and can scale to hundreds of thousands, perhaps millions, of nodes with maximum latencies as low as two network hops and high bisection bandwidths  ...  In general, low-diameter networks can be built out to 1,000,000 nodes with a modest number of ports: high-diameter Flattened Butterfly designs and Fishnet designs will scale to these sizes in under 30  ... 
doi:10.1145/2989081.2989130 dblp:conf/memsys/LiHBDEHRRWAJ16 fatcat:nnx4vczn7zby5pwten5c2l2wtm

Silicon-photonic clos networks for global on-chip communication

Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Imran Shamim, Krste Asanovic, Vladimir Stojanovic
2009 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip  
In this paper we explore using photonics to implement low-diameter non-blocking crossbar and Clos networks.  ...  Siliconphotonics is a promising new interconnect technology which offers lower power, higher bandwidth density, and shorter latencies than electrical interconnects.  ...  Acknowledgments This work was supported in part by Intel Corporation and DARPA awards W911NF-08-1-0134 and W911NF-08-1-0139.  ... 
doi:10.1109/nocs.2009.5071460 dblp:conf/nocs/JoshiBKBSAS09 fatcat:35dvnktybzbotg65bcdcmlg62a

High-radix on-chip networks with low-radix routers

Animesh Jain, Ritesh Parikh, Valeria Bertacco
2014 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
While high-radix routers enable a richly connected and low diameter network, low-radix routers allow for a small silicon area.  ...  In this work, we present a novel solution to provide high-radix like performance at a cost similar to that of a low-radix network.  ...  With HiROIC we want to provide the best of both classes: the effective network diameter of high-radix topologies and the low resource requirements of low-radix networks.  ... 
doi:10.1109/iccad.2014.7001365 dblp:conf/iccad/JainPB14 fatcat:3chfvjvew5gqtofzcxyko2h4mq

Dodec: Random-Link, Low-Radix On-Chip Networks

Haofan Yang, Jyoti Tripathi, Natalie Enright Jerger, Dan Gibson
2014 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture  
As a proof-of-concept for random on-chip topologies, we explore a novel set of networks -dodecs -and illustrate how they reduce network diameter with randomized low-radix router connections.  ...  We propose a methodology to design random topologies for on-chip networks. Random topologies provide better scalability in terms of network diameter and provide inherent load balancing.  ...  We thank Peter Klausler for positing the idea of a dodecahedronshaped on-chip network.  ... 
doi:10.1109/micro.2014.19 dblp:conf/micro/YangTJG14 fatcat:4r33bidfevbzlds3aogoa4vnsu

3D-TTN: a power efficient cost effective high performance hierarchical interconnection network for next generation green supercomputer

Faiz Al Faisal, M. M. Hafizur Rahman, Yasushi Inoguchi
2021 Cluster Computing  
On the other hand, hierarchical interconnection networks (like-3D-TTN) can be a possible solution to those issues.  ...  According to our power-performance results, 3D-TTN can also show better result than the 3D-Mesh, 2D-Mesh, 2D-Torus and 3D-TESH network even at the lowest network level.  ...  Moreover, it is expected to link power will have also have a large impact in comparing with 3D-TTN (router radix is 8) as the router radix for 5D-Torus is 10.  ... 
doi:10.1007/s10586-021-03297-1 pmid:34031630 pmcid:PMC8133524 fatcat:dmekikzkevbqbp5atozacbicmu

Generic Low-Latency NoC Router Architecture for FPGA Computing Systems

Ye Lu, John McCanny, Sakir Sezer
2011 2011 21st International Conference on Field Programmable Logic and Applications  
A novel cost-effective and low-latency wormhole router for packet-switched NoC designs, tailored for FPGA, is presented.  ...  A key feature is that it achieves a low packet propagation latency of only two cycles per hop including both router pipeline delay and link traversal delay -a significant enhancement over existing FPGA  ...  The attraction of high-radix routers with high levels of connectivity is that hop numbers can be significantly reduced with the network diameter.  ... 
doi:10.1109/fpl.2011.25 dblp:conf/fpl/LuMS11 fatcat:itdlmvmyibenrjtmhxk3dyc6ei
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