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A low-power high-speed true single phase clock divide-by-2/3 prescaler

Jianhui Wu, Zixuan Wang, Xincun Ji, Cheng Huang
2013 IEICE Electronics Express  
A novel low power high-speed true single-phase clockbased (TSPC) divide-by-2/3 prescaler is presented.  ...  By modifying the precharge branch in the TSPC flip-flop instead of the AND gate in conventional topologies, the inverter between the two flip-flops of the conventional divide-by-2/3 prescaler is eliminated  ...  Conclusion In this paper, a new high-speed and low-power divid-by-2/3 prescaler is presented.  ... 
doi:10.1587/elex.10.20120913 fatcat:ibkwsbnfkjebnm326b4zut7poy

A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler

Wenjian Jiang, Fengqi Yu, Qinjin Huang
2017 IEICE Electronics Express  
A novel low-power high-speed true single-phase clock-based (TSPC) divide-by-2/3 prescaler is presented.  ...  The prescaler is implemented in a standard 0.18-µm CMOS process.  ...  In this paper, a novel high-speed low-power divide-by-2/3 prescaler based on TSPC DFF has been proposed.  ... 
doi:10.1587/elex.13.20160446 fatcat:w6xfa4nlhzhtffzm4vhc53wxly

Power Optimized Divide-By-2/3 Counter Based Clock Design Using Multiplexer

Anandkumar. M
2013 IOSR Journal of Engineering  
This paper proposes a advanced method of extended true-single-phase-clock (E-TSPC) based divideby-2/3 counter design for providing low supply voltage and low power consumption.  ...  The E-TSPC Prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications.  ...  FF based divide-by -N/N+1 designs adopt dynamic logic FFs such as true-single-phase clock (TSPC).  ... 
doi:10.9790/3021-03151422 fatcat:rwllak66cvdbjbkirjbfzcjyma

High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler

Xiaoran Li, Jian Gao, Zhiming Chen, Xinghua Wang
2020 Electronics  
This manuscript presents two novel low-power high-speed true-single-phase-clock (TSPC) prescalers with division ratios of 2/3 and 4/5, respectively, in a standard 90-nm CMOS technology.  ...  The power of the proposed divide-by-2/3 prescaler is 0.67 mW and 0.92 mW, and 0.87 mW and 1.06 mW for the proposed divide-by-4/5 prescaler.  ...  Figure 1 . 1 (a) Block diagram and (b) schematic of the conventional true-single-phase-clock (TSPC) divide-by-2/3 prescaler.  ... 
doi:10.3390/electronics9050725 fatcat:ypqdvct6djgipkolcmn47n4mca

A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler

Xincun Ji, Xiaojuan Xia, Zixuan Wang, Leisheng Jin
2017 IEICE Electronics Express  
A TSPC dual-modulus prescaler is proposed to reduce the PLL's power consumption by merging one of the branches of the true single-phase clocked (TSPC) D flip-flops.  ...  The measured synthesizer output frequency ranges from 2.16 to 2.7 GHz, and consumes 8 mW from a 1.3 V power supply.  ...  Fig. 2 . 2 Conventional divide-by-2/3 prescaler from [7] Fig. 3 . 3 Proposed divide-by-2/3 prescaler and topology 4 Other building blocks of the PLL The circuits of the VCO and the charge pump are  ... 
doi:10.1587/elex.14.20170065 fatcat:flwtc6va4zgcvdulkp7buqcjja

A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs

Tianchen Shen, Jiabing Liu, Chunyi Song, Zhiwei Xu
2019 Electronics  
A high-speed, low-power divide-by-3/4 prescaler based on an extended true single-phase clock D-flip flop (E-TSPC DFF) is presented.  ...  The measurement results demonstrate that the proposed divider achieves high-speed and low-power operation.  ...  The output frequency of a divide-by-2/3 prescaler is higher than a divide-by-3/4 prescaler.  ... 
doi:10.3390/electronics8050589 fatcat:zpjixkpgcrc53hh73wrnxbf5gi

A Power Optimized Divide by N Prescaler Design on 50nm CMOS Process

Nityanand Urmaliya, Prof. Shravan Kumar Sable
2017 IJARCCE  
In order to attain high operating frequency a high speed parallel counter is presented.  ...  The operation speed is improved by reduction of the critical path delay and the low power consumption can be achieved due to less number of interconnects.  ...  In [2] divide-by-2/3 counter design for low supply voltage and low power consumption applications is discussed.  ... 
doi:10.17148/ijarcce.2017.6616 fatcat:gxvqcksfu5fjdkdsi5jup4rudm

A 1.8-V 6.5-GHz low power wide band single-phase clock CMOS 2/3 prescaler

M.Vamshi Krishna, M.A. Do, C.C. Boon, K.S. Yeo, Wei Meng Lim
2010 2010 53rd IEEE International Midwest Symposium on Circuits and Systems  
In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-2/3 prescaler is investigated.  ...  Index Terms-DFF, frequency synthesizer, E-TSPC, true single-phase clock(TSPC), high speed digital circuits, Dual modulus prescalers.  ...  E-TSPC 2/3 prescaler in Alternatively, flip-flop based prescalers can be designed using dynamic logic flip-flops such as true single-phase clock (TSPC) [5] and extended true single-phase clock [6] .  ... 
doi:10.1109/mwscas.2010.5548580 fatcat:lgkkw64zmjetpn7rejoyqxiyfq

Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler

M.V. Krishna, Manh Anh Do, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng Lim
2010 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
ACKNOWLEDGMENT The authors would like to thank A. Do, A. Cabuk, X. Juan, and G. Jiangmin of the RF Group and A. Meaamar for their valuable discussion and advice.  ...  In a conventional divide-by-2/3 TPSC prescaler, DFF1 is loaded only by an OR gate, while DFF2 is loaded by an AND gate, DFF1 and an output stage making up a much larger load.  ...  Therefore, dynamic and sequential circuit techniques or clocked logic gates such as, true single phase clocks [1] - [4] , must be used in designing synchronous circuits to reduce circuit complexity,  ... 
doi:10.1109/tcsi.2009.2016183 fatcat:kuz5hukydjbflmvqd6bhlbtbey

High-speed divide-by-4/5 prescalers with merged and gates using GaInP/GaAs HBT and SiGe HBT technologies

Hung-Ju Wei, Chinchun Meng, YuWen Chang, Yi-Chen Lin, Guo-Wei Huang
2008 Microwave and optical technology letters (Print)  
At the supply voltage of 5 V, the GaInP/GaAs prescaler operates from 30 MHz to 5.2 GHz, and the SiGe prescaler has the higher-speed performance of 1-8 GHz at the cost of power consumption.  ...  By biasing the HBT near the peak transit-time frequency (f T ), the maximum operating frequency of a D-type flip-flop can be promoted.  ...  This kind of synthesizer generally uses the dual-modulus prescaler with the programmable divide-by-N/N ϩ 1 to achieve the fractional-N function, such as divide-by-2/3 or divide-by-4/5 prescaler.  ... 
doi:10.1002/mop.23407 fatcat:cvz4ym4gwrff3fgfrw3lsyyaue

Design of Low Noise 10 GHz divide by 16…511 Frequency Divider

M. Jurgo, K. Kiela, R. Navickas
2013 Elektronika ir Elektrotechnika  
Extended True Single Phase Clock (ETSPC) logic is used for 2/3 dividers to achieve high input frequency and low power and TSPC logic is used for 6-bit counter.  ...  Main blocks of the divider are three-stage dual modulus divide by 2/3 divider chain, 6-bit counter, jitter removal and synchronisation flip-flops.  ...  The key blocks are three-stage divide-by-2/3 dual modulus prescaler chain and 6-bit programmable down counter.  ... 
doi:10.5755/j01.eee.19.6.4570 fatcat:ogkbhnk7wjgebpd7y6vshobafi

A Programmable Frequency Divider with Wide Division Ratio and Input Frequency Range

Yilong Liao, Xiangning Fan, Yongjian Shi
2019 IOP Conference Series: Earth and Environment  
By using the divider-by-2/3 chain, the division ratio of the whole programmable frequency divider covers from 256 to 510.  ...  A programmable frequency divider with wide input frequency and divison ratio range is designed in 65nm TSMC RF CMOS technology and presented in this paper.  ...  The D-latch used in the divide-by-2/3 cell can be CMOS static logic, true single phase clock(TSPC) logic, and current mode logic (CML).  ... 
doi:10.1088/1755-1315/234/1/012103 fatcat:adslercx45endkkdad6xg4zb6i

A 12GHz programmable fractional-n frequency divider with 0.18um CMOS technology

Siavash Heydarzadeh, Pooya Torkzadeh, Mohammad Pourmina
2013 2013 5th Computer Science and Electronic Engineering Conference (CEEC)  
., 8) extended True-Single-Phase-Clock (E-TSPC) frequency dividers with 0.18µ CMOS technology and TSMC process is presented.  ...  The E-TSPC circuits have a small area occupation, extremely low power consumption (less than 220µW from 1.8V supply voltage) and 50% duty-cycle sinusoidal output voltage.  ...  Anbarasi, 2012. capacitance and achieving a high sinusoidal output Design of power efficient divide by 2/3 counter using swing).  ... 
doi:10.1109/ceec.2013.6659440 fatcat:dvobncns75fuphhu5csj2xmgvm

Low Power 24 GHz ad hoc Networking System Based on TDOA for Indoor Localization

Melanie Jung, Georg Fischer, Robert Weigel, Thomas Ussmueller
2013 ISPRS International Journal of Geo-Information  
This paper introduces the key elements of a novel low-power, high precision localization system based on Time-Difference-of-Arrival (TDOA) distance measurements.  ...  The comparison of the first and second generation of the system shows a significant size and power reduction as well as an increased precision.  ...  The generic MMD architecture includes a number of cascaded divide-by-2/3 cells.  ... 
doi:10.3390/ijgi2041122 fatcat:j5lytg5ecvh3pofe22w7nm55kq

A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers

Ching-Yuan Yang
2008 Analog Integrated Circuits and Signal Processing  
The D flip-flop and logic flip-flop are proposed by using a fast pipeline technique, which contains single-phase, edge-triggered, ratioed, and high-speed technologies.  ...  A high-frequency divide-by-256-271 programmable divider is presented with the improved timing of the multi-modulus divider structure and the high-speed embedded flip-flops.  ...  Conventionally, a highspeed programmable divider is implemented using an extension of a dual-modulus divider in which the overall divide-by-2 sections are replaced with divide-by-2/3 blocks [4, 13] .  ... 
doi:10.1007/s10470-008-9159-8 fatcat:6umljdsctrhqdcvpfwaqm2heqm
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