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A low-complexity issue logic

Ramon Canal, Antonio González
2000 Proceedings of the 14th international conference on Supercomputing - ICS '00  
In this work, two new issue schemes that reduce the hardware complexity of the issue logic with minimal impact on the average number of instructions executed per cycle are presented.  ...  One of the main concerns in today's processor design is the issue logic.  ...  These approaches try to reduce the complexity of the issue logic by partitioning it into several parts.  ... 
doi:10.1145/335231.335263 dblp:conf/ics/CanalG00 fatcat:56nxzdscyfeddemxhw5xgp7xoa

Low Complexity Out-of-Order Issue Logic Using Static Circuits

Siddhesh S. Mhambrey, Satendra K. Maurya, Lawrence T. Clark
2013 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Researchers at Arizona State University have developed a new method to reduce issue logic complexity.  ...  Despite these advantages however, there is still demand for more efficient and less complex methods to resolve issue logic complexity.  ...  a new method to reduce issue logic complexity.  ... 
doi:10.1109/tvlsi.2012.2184310 fatcat:2ws5o2y4ivbandtmyagvnqgwfm

Low-power, low-complexity instruction issue using compiler assistance

Madhavi G. Valluri, Lizy K. John, Kathryn S. McKinley
2005 Proceedings of the 19th annual international conference on Supercomputing - ICS '05  
This paper develops a cooperative hardware/software technique to reduce complexity and energy consumption of the issue logic.  ...  The logic that facilitates dynamic issue is one of the most power-hungry and time-critical components in a typical out-of-order issue processor.  ...  The resulting issue logic is thus significantly lower in power and complexity when compared to a conventional issue queue.  ... 
doi:10.1145/1088149.1088177 dblp:conf/ics/ValluriJM05 fatcat:p7so5hj7fbglldm3br67prfxhi

Complex systems and networks with their applications

Jin-de Cao, Yang Liu, Jian-quan Lu, Leszek Rutkowski
2020 Frontiers of Information Technology & Electronic Engineering  
In this context, the Chinese Academy of Engineering (CAE) organized a special issue of Frontiers of Information Technology & Electronic Engineering, focusing on complex systems and networks with their  ...  After a rigorous review process, 12 papers by researchers worldwide have been selected for this special issue, including two survey papers and 10 research papers.  ...  a set stabilization issue.  ... 
doi:10.1631/fitee.2020000 fatcat:cj7r5nao7rg2jokweqvczkmckm

Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-based Scheduling

Kuo-Su Hsiao, Chung-Ho Chen
2006 Computer Design (ICCD '99), IEEE International Conference on  
In a high-performance superscalar processor, the instruction scheduler comes with poor scalability and high complexity due to the inefficient and costly instruction wakeup operation.  ...  From simulation-based analyses, we find that 98% of the wakeup activities are useless in the conventional wakeup logic.  ...  These schedulers replace the complex wakeup logic with a simple FIFO queue. On the other hand, Brown et al. presents the select-free scheduler [17] .  ... 
doi:10.1109/iccd.2006.4380817 dblp:conf/iccd/HsiaoC06 fatcat:p2undxnryzfurlmho7xosly2xm

A Simplex Architecture for Intelligent and Safe Unmanned Aerial Vehicles

Prasanth Vivekanandan, Gonzalo Garcia, Heechul Yun, Shawn Keshmiri
2016 2016 IEEE 22nd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)  
Keshmiri's lab in KU Aerospace Engineering -Fixed wing (DG 808, G1XD, G1XB) and a Quadcopter -Nvidia Tegra TK1, 4 x ARM Cortex-A15 @ 2.3GHz, 192 core GPU -28nm process, > a billion transistors  complex  ...  Robust and Adaptive Control • Advanced adaptive non-linear model predictive controller (NMPC) Common Issues in UAVs • Divergence or low quality state estimations by the EKF due to external factors such  ... 
doi:10.1109/rtcsa.2016.17 dblp:conf/rtcsa/VivekanandanGYK16 fatcat:q5mhlzqiifadhhalosithnl3sq

Logic between Expressivity and Complexity [chapter]

Johan van Benthem
2010 Lecture Notes in Computer Science  
I will discuss some key issues. This text is just an appetizer that will be elaborated in the lecture.  ...  Automated deduction is not just application or implementation of logical systems. The field of computational logic also poses deep challenges to our understanding of logic itself.  ...  Philosophy: low complexity may not be needed, since a key aspect of rationality is a talent for exercising 'judgment' in using a potentially dangerous tool.  ... 
doi:10.1007/978-3-642-14203-1_10 fatcat:jvshiaftbja3hpd53lkrz5p3zi

Energy Efficient Multiplier Design Using Gdi Logic

K.Sai srilakshm, V. Nancharaiah, Ch. Karthik, K. Jagadeesh
2017 IOSR Journal of Electronics and Communication Engineering  
The goal is to proposed full adders extended with multiplier to reduce the complexity of design as well as make a low energy consumption and high speed in designing systems.  ...  These issues can be overcome by new technique GATE DIFFUSION INPUT (GDI) logic technique which is commonly occurring a threshold voltage problem, so it does not allow adders without additional inverters  ...  This technique allows reducing power consumption, delay and area of a low power digital circuits, while maintaining low complexity of logic design[12]. II.  ... 
doi:10.9790/2834-1202033339 fatcat:blotgkawaff2dlrofrxdtaxd2e

14 Transistors CNTFET and CMOS Full Adder Cell for Modified GDI Technique

The Main Issue In Design High Speed Full Adder Cell With The Low Power Dissipation. As We Know Cmos Technology Used For Vlsi Designing Cmos Has Many Drawbacks As High Power Short Channel Effect Etc.  ...  GDI used to implement low power logical circuit and also simplify the complex logic with less count of transistor.  ...  GDI technique is used to simplify the complex logic. GDI cell is best structure for high speed and low power logic. GDI also reduce the chip area by decrease the count of transistor [10] [11] .  ... 
doi:10.35940/ijitee.l3233.1081219 fatcat:6wy4zlor6ne4vf4oye54s6bwfa

Special issue on automated deduction: Decidability, complexity, tractability

Silvio Ghilardi, Viorica Sofronie-Stokkermans, Ulrike Sattler, Ashish Tiwari
2010 Journal of symbolic computation  
to be considered, which are decidable and sometimes even have low complexity.  ...  Decidability and complexity issues are extremely important in automated deduction.  ... 
doi:10.1016/j.jsc.2009.05.006 fatcat:ojjvruw2jza6tpamkmmgyfk3cq

Design of Efficient Complex Gate using 45nm Technology

Now-a-days Efficient Complex Gate using 45nm technology is preferable because of its delay and power.  ...  In this paper, we designed complex gate which is having very good performance in terms of delay. This is achieved by increasing threshold voltage.  ...  A short circuit path will be created between Vdd & output for high logic of input and for low logic of input a shorted path will takes place between Vss and Gnd. IV.  ... 
doi:10.35940/ijitee.b7569.129219 fatcat:2547lmyd6vcvhhjbjxgiz2eux4

Design and Simulation of High Speed CMOS Full Adder

V.Vinay kumar, V.Viswa nadha
2014 International Journal of Engineering Trends and Technoloy  
Therefore, 1-bit Full Adder cell is the most important and basic block of an arithmetic unit of a system.  ...  uses transmission gate logic to realize complex logic functions using a small number of complementary transistors.  ...  DESIGN CONSIDERATIONS A. Impact of Logic Style: The logic style used in logic gates basically influences the speed, size, power dissipation, and the wiring complexity of a circuit.  ... 
doi:10.14445/22315381/ijett-v15p237 fatcat:zai6epcscnbqflh2m6ftbbndbu

Book review

Timothy J. Ross
2007 Artificial Intelligence  
The reason is simple: fuzzy logic is the logic used in systems of high complexity (as opposed to binary logic's use in systems of low complexity), and such systems require methods to reduce, in some sense  ...  A very simple system does not need fuzzy logic for its description or use.  ...  The reason is simple: fuzzy logic is the logic used in systems of high complexity (as opposed to binary logic's use in systems of low complexity), and such systems require methods to reduce, in some sense  ... 
doi:10.1016/j.artint.2007.10.003 fatcat:aod6akobebcl7nk4cdzmfk6yji

Title index to volume 6

1989 The Journal of Logic Programming  
, 135 Computable Semantics for General Logic Programs, A, 269 Extending SLD Resolution to Equational Horn Clauses Using E-Unification, 3 High-Performance Low Rise Machine for Logic Pro- gramming  ...  TITLE INDEX TO VOLUME 6Logical Analysis of Modules in Logic Programming, A, 79Term Matching on Parallel Computers, 213 Third IEEE Symposium on Logic Programming: Special Issue, 6(l),(2) Compiling Control  ... 
doi:10.1016/0743-1066(89)90018-6 fatcat:yydlupw2zvftvn3vvaij7p3c7y

Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era

Aida Todri-Sanial, Saraju P. Mohanty, Mariane Comte, Marc Belleville
2017 ACM Journal on Emerging Technologies in Computing Systems  
Such large fault tolerance further motivates design of complex arithmetic logic at reduced implementation cost.  ...  The papers presented in this issue span through various design challenges from devices, circuits and architecture to address some of the most imminent issues for low power computing.  ... 
doi:10.1145/3003370 fatcat:7kw7ei7tnnas3jqgxke73rakiy
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