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A low power switching power supply for self-clocked systems

Gu-Yeon Wei, M. Horowitz
Proceedings of 1996 International Symposium on Low Power Electronics and Design  
Sparso and K. van Berkel, "Low-Power Operation Using Self-Timed Circuits and Adaptive Scaling of Supply Voltage," IEEE Trans. on VLSI Systems, vol 2, no. 4, pp. 391-397, Dec. 1994. [2] P.  ...  Oguey, "A Voltage Reduction Technique for Digital Systems," IEEE ISSCC 1990 Dig. Tech. Papers, pp. 238-239, Feb. 1990.  ...  Conclusion In this paper we have explored the potential of designing a digital power supply controller for self-clocked systems to improve energy efficiency.  ... 
doi:10.1109/lpe.1996.547531 dblp:conf/islped/WeiH96 fatcat:l4sswjtz4zhszfplsgygmve6ny

Fast, efficient, recovering, and irreversible

Visvesh Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou
2005 Proceedings of the 2nd conference on Computing frontiers - CF '05  
-SPLE'94 • Clock-powered CMOS: A hybrid adiabatic logic style for energy-efficient computing N. Tzartzanis and W. C. Athas -ARVLSI'99 And many, many others....  ...  Resonate entire clock capacitance with small inductor Pump resonant system with NMOS switch at appropriate times NMOS switch only conducts incremental losses whenever "on" NMOS Switch Control  ... 
doi:10.1145/1062261.1062330 dblp:conf/cf/SatheCKZKP05 fatcat:pf7vqgqc2fbpnhluml6g4qq5ku

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits [chapter]

A.J. Acosta, R. Jiménez, J. Juan, M.J. Bellido, M. Valencia
2000 Lecture Notes in Computer Science  
However, static power consumption is the main penalty of such structures, making them unsuited for low-power applications.  ...  clock-phase and asynchronous styles for reducing switching noise.  ...  Fig. 2 . 2 Different clocking styles for a pipelined logic structure: a) Single-phase, b) Two phases, c) Self-timed. The dashed areas in the Activity bar indicate the maximum switching density.  ... 
doi:10.1007/3-540-45373-3_33 fatcat:37rr2bvbenbwrawoqh5mzgx2wu

A 225 MHz resonant clocked ASIC chip

Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
Our chip comprises a dual-mode ASIC with two independent clock systems, one conventional and one energy recovering, and was fabricated in a 0.25µm bulk CMOS process.  ...  In the energy recovering mode, our power measurements account for all of the dissipation factors, including the operation of the integrated resonant clock generator, and show a net energy savings over  ...  The power-clock node P clk supplies both power and timing information to the circuit, in contrast to conventional clock nodes which supply only timing information.  ... 
doi:10.1145/871522.871523 fatcat:w3iiei64vzcgjiufnf237fmaky

A 225 MHz resonant clocked ASIC chip

Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
Our chip comprises a dual-mode ASIC with two independent clock systems, one conventional and one energy recovering, and was fabricated in a 0.25µm bulk CMOS process.  ...  In the energy recovering mode, our power measurements account for all of the dissipation factors, including the operation of the integrated resonant clock generator, and show a net energy savings over  ...  The power-clock node P clk supplies both power and timing information to the circuit, in contrast to conventional clock nodes which supply only timing information.  ... 
doi:10.1145/871506.871523 dblp:conf/islped/ZieslerKSP03 fatcat:euvxs2jblnfzvpxu7g6qo2esvu

A 3-pin 1.5 V 550 mW 176 x 144 self-clocked CMOS active pixel image sensor

Kwang-Bo Cho, Alexander Krymski, Eric Fossum
2001 Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01  
This paper addresses the development of a micropower 176 x 144 self-clocked CMOS active pixel image sensor that dissipates oneto-two orders of magnitude less power than current state of the art CMOS image  ...  The chip operates from a 1.5 V voltage source and the power consumption measured for the chip running from an internal 25.2 MHz clock yielding 30 frames per second is about 550 µW.  ...  For power reduction through circuit/logic design, reduction of the power supply voltage can be a key element in low-power CMOS image sensors.  ... 
doi:10.1145/383082.383176 dblp:conf/islped/ChoKF01 fatcat:o4yjfuw2fngldawxywdnm6f7kq

A Study of 3-D Power Delivery Networks With Multiple Clock Domains

Aida Todri-Sanial, Yuanqing Cheng
2016 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
This paper proposes an efficient analysis for assessing the worst case power supply noise on 3-D power delivery networks (PDNs) with multiple clock domains.  ...  This paper presents a summary of guidelines for modeling, analyzing, and exploring a design of reliable 3-D PDNs with multiple clock domains.  ...  We evaluate the power supply noise for each type of TSV while applying the same switching activity and frequency to the 3-D system.  ... 
doi:10.1109/tvlsi.2016.2549275 fatcat:dunjxsogqrf3hg7s5g7fn4g5dq

Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect

Yuanqing Cheng, Aida Todri-Sanial, Jianlei Yang, Weisheng Zhao
2016 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
This paper proposes an efficient analysis for assessing the worst case power supply noise on 3-D power delivery networks (PDNs) with multiple clock domains.  ...  This paper presents a summary of guidelines for modeling, analyzing, and exploring a design of reliable 3-D PDNs with multiple clock domains.  ...  We evaluate the power supply noise for each type of TSV while applying the same switching activity and frequency to the 3-D system.  ... 
doi:10.1109/tvlsi.2016.2543260 fatcat:5ja53fglqfd7toafwkthogaawe

Energy harvesting and limits of low power mixed-signal circuit design

Rajeevan Amirtharajah, Justin Wenck, Nathaniel Guilar
2009 2009 IEEE International Symposium on Circuits and Systems  
Wireless sensors and implantable medical devices have driven IC design to extremes of low power consumption to maximize system operating lifetimes from fixed energy stores or from energy harvested from  ...  We describe three key sensor subsystems: integrated diodes for solar energy harvesting, efficient microwatt power conversion circuits, and supply-voltage-ripple-tolerant digital circuits.  ...  Kleeburg for their contributions to this work, and our colleagues and collaborators S. Bruss and Profs. P. Hurst, A. Knoesen, S. Lewis, and D. Yankelevich.  ... 
doi:10.1109/iscas.2009.5118033 dblp:conf/iscas/AmirtharajahWG09 fatcat:7xdj2cxhpbenthjn5rnua4daom

Low-voltage DC-DC converter for IoT and on-chip energy harvester applications

Miroslav Potocny, Martin Kovac, Daniel Arbet, Michal Sovcik, Lukas Nagy, Viera Stopjakova, Richard Ravasz
2021 Zenodo  
The presented converter could also employ the on-chip RF-based energy harvester for use in a wireless power transfer system.  ...  The charge pump utilizes a power-efficient ON/OFF regulation feedback loop, especially designed for strict low-voltage start-up conditions by a driver booster.  ...  In such a case, the efficiency of the self-powered CP system is less dependent 371 on the clock frequency.  ... 
doi:10.5281/zenodo.5526446 fatcat:nzgynowsfjesncohqd5xqcmj3e

PERFORMANCE ANALYSIS OF POWER GATING TECHNIQUES IN 4-BIT SISO SHIFT REGISTER CIRCUITS

K. NEHRU, C. DEEPTHI, S. SUSHMA, S. SARAVANAN
2017 Journal of Engineering Science and Technology  
demonstrate that minimum power consumption can be achieved when the adder and SISO are designed for clock gating.  ...  A 4 bit SISO and full adder was designed in a cadence virtuoso 180 nm technology and the simulated results show the trade-off between power, delay and power for the sequential circuits and the results  ...  The basic idea is to shut down power supply for idle systems. This is done by using high threshold transistors.  ... 
doaj:7cf6e70429b04654894f846d7614ef57 fatcat:dp5tb5w5lnfmzbrs2njiljetve

Elements of low power design for integrated systems

Sung-Mo Kang
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
In this paper, we discuss major sources of power dissipation in VLSI systems, and various low power design techniques on the technology and circuit level, logic level, and system level.  ...  The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative developments in low power  ...  Also the author is grateful for Gordon Mortensen of National Semiconductor Company and Prof. A. M. Ionescu for providing helpful data.  ... 
doi:10.1145/871506.871558 dblp:conf/islped/Kang03 fatcat:nqdffwcb7fclnhc2uuqpwyw3qa

An EMI Reduction Technique for Digitally Controlled SMPS

Olivier Trescases, Guowen Wei, Aleksandar Prodic, Wai Tung Ng
2007 IEEE transactions on power electronics  
A spread spectrum technique and system for reducing average electromagnetic interference (EMI) in low-power digitally controlled dc-dc switch-mode power supplies (SMPS) are introduced.  ...  The change is performed with a 1-b 16 digital-to-analog converter. Compensator design guidelines for this variable frequency system are provided for obtaining good dynamic response.  ...  Dedicated spread spectrum clock synthesizers integrated circuit (IC)-s [8] , developed for analog controlled low-power SMPS, could potentially be combined with some of the existing low-power digital controllers  ... 
doi:10.1109/tpel.2007.901911 fatcat:cddsfygsnben5eljnsnhusnuiu

Low-Voltage DC-DC Converter for IoT and On-Chip Energy Harvester Applications

Miroslav Potocny, Martin Kovac, Daniel Arbet, Michal Sovcik, Lukas Nagy, Viera Stopjakova, Richard Ravasz
2021 Sensors  
The presented converter can also employ the on-chip RF-based energy harvester for use in a wireless power transfer system.  ...  The charge pump utilizes a power-efficient ON/OFF regulation feedback loop, specially designed for strict low-voltage start-up conditions by a driver booster.  ...  In such a case, the efficiency of the self-powered CP system is less dependent on the clock frequency.  ... 
doi:10.3390/s21175721 pmid:34502611 pmcid:PMC8433648 fatcat:jllx7ebxsvhsbjkzxlar3fanjq

Elements of low power design for integrated systems

Sung-Mo Kang
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
In this paper, we discuss major sources of power dissipation in VLSI systems, and various low power design techniques on the technology and circuit level, logic level, and system level.  ...  The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative developments in low power  ...  Also the author is grateful for Gordon Mortensen of National Semiconductor Company and Prof. A. M. Ionescu for providing helpful data.  ... 
doi:10.1145/871557.871558 fatcat:dqp4gercknfvrf65vbx2mlozeu
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