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Design and Power Measurement of 2 And 8 Point FFT Using Radix-2 Algorithm for FPGA Implementation

Mayura Patrikar, Prof.Vaishali Tehre
2017 IOSR Journal of VLSI and Signal processing  
In this paper given to design and power measurement 2 and 8 point FFT by using VHDL. Simulation and synthesis of design is done using Xilinx ISE 14.2.  ...  FFT algorithms uses many applications for example, OFDM, Noise reduction, Digital audio broadcasting, Digital video broadcasting. It's used to design butterflies for different point FFT.  ...  Vaishali A. Tehre, with a heartfelt gratitude for the valuable and persistent guidance given by her through formal information, discussion, support and timely inspiration.  ... 
doi:10.9790/4200-0701014448 fatcat:mkehlu7auffg5ccr35oteu5iy4

Design and Evaluation of a Scalable Engine for 3D-FFT Computation in an FPGA Cluster

Roberto Ammendola, Pierpaolo Loreti
2019 International Journal on Advanced Science, Engineering and Information Technology  
We devise a scalable FFT engine based on a custom radix-2 doubleprecision core that is used to implement the Decimation in Frequency version of the Cooley-Tukey FFT algorithm.  ...  In this paper, we explore an HPC design that uses FPGA accelerators to compute the 3DFFT.  ...  Considering that modern FPGAs have the considerable processing power, the paper investigates the possibility of using the networking FPGA as a hardware accelerator for computing of the 3D FFT.  ... 
doi:10.18517/ijaseit.9.2.8308 fatcat:mprbnwfrqbcarfpxkg6ovrqaem

FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

Yeongung Choi, Dongmin Jeong, Myeongjin Lee, Wookyung Lee, Yunho Jung
2021 Electronics  
Therefore, the proposed RDA-based SAR processor contains an MFU that uses the mixed-radix multi-path delay commutator (MRMDC) FFT and an RPU.  ...  In this paper, we propose a range-Doppler algorithm (RDA)-based synthetic aperture radar (SAR) processor for real-time SAR imaging and present FPGA-based implementation results.  ...  gratefully acknowledge the support from the Next-Generation SAR Research Laboratory at Korea Aerospace University, originally funded by the Defense Acquisition Program Administration (DAPA) and Agency for  ... 
doi:10.3390/electronics10172133 fatcat:ml522p6wkfh7tfay6qbmk5iikq

Research on heterogeneous acceleration platform based on FPGA

Yuan Meng, Jun Yang, L. Wang
2022 ITM Web of Conferences  
Then the paper proposed the design of the FPGA-CPU heterogeneous acceleration platform, and introduced the base-two-FFT algorithm.  ...  Although scaling distributed clusters horizontally to cope with the increasing demands on computing power for massive data processing is feasible.  ...  The top-level design framework of a heterogeneous Spark cluster. Fig 4 . 4 Fig 4. Diagram of radix-2 FFT processing engine. Fig. 5 . 5 Fig. 5. Radix-2 FFT simulation of 2MHz signal.  ... 
doi:10.1051/itmconf/20224501029 fatcat:wmnjvcadifdvlh6azipebej45a

Implementation techniques of high-order FFT into low-cost FPGA

Yousri Ouerhani, Maher Jridi, A. Alfalou
2011 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)  
For this reason, we propose to optimize existing FFT algorithms for low-cost FPGA implementations. For that, we have used short length structures to obtain higher length transforms.  ...  Firstly, the radix-4 FFT is modified to process one sample per clock cycle.  ...  timing diagram Fig. 5 . 5 Residual Power between matlab simulation and real performance on FPGA TABLE I 64 I -POINT FFT LATENCY COMPARAISON Low Latency Low Area [4] design of Fig. 2 Xilinx IP design  ... 
doi:10.1109/mwscas.2011.6026390 fatcat:vxarki7nkngtjn65wutbew2fzm

Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform [chapter]

K. Masselos, S. Blionas, J-Y. Mignolet, A. Foster, D. Soudris, S. Nikolaidis
2004 Lecture Notes in Computer Science  
An AMDREL platform based reconfigurable SoC for a multi-mode wireless networking system is currently under development.  ...  The platform's main building blocks are presented, including coarse grain reconfigurable unit, embedded FPGA, interconnection network and application specific reusable blocks.  ...  Disclaimer The information in this document is provided as is and no guarantee or warranty is given that the information is fit for any particular purpose.  ... 
doi:10.1007/978-3-540-30205-6_63 fatcat:qjqoavk3erepfe22j7xvkkbr4q

Spectral Method Characterization on FPGA and GPU Accelerators

Karl Pereira, Peter Athanas, Heshan Lin, Wu Feng
2011 2011 International Conference on Reconfigurable Computing and FPGAs  
For fixed-point FFTs, however, FPGAs exploit a flexible data path width to trade-off circuit cost with speed of computation in applications requiring smaller precision to improve performance, power and  ...  This paper compares the sustained performance of a complex, single precision, floatingpoint, 1D, Fast Fourier Transform (FFT) implementation on state-of-the-art FPGA and GPU accelerators.  ...  of Xilinx for supporting the work.  ... 
doi:10.1109/reconfig.2011.83 dblp:conf/reconfig/PereiraALF11 fatcat:hf6jnvqzkvfppel262z3lscbra

System-on-Chip Subband Decomposition Architectures for Ultrasonic Detection Applications

Erdal Oruklu, Joshua Weber, Jafar Saniie
2011 Journal of Signal Processing Systems  
A comparative study and performance results present the advantages of the recursive hardware architecture compared to the conventional implementation of the SSP algorithm using IP cores for FFT.  ...  The SSP design is realized using recursive subband decomposition techniques for achieving minimal hardware and power consumption.  ...  A hardware/software (HW/SW) codesign implementation Algorithm stage HW/SW codesign (with FFT accelerator) Hardware radix-4 FFT Hardware radix-2 FFT Hardware Goertzel DFT (5 filter kernels  ... 
doi:10.1007/s11265-011-0623-9 fatcat:nwttgv44v5atfp5nc2235ov62i

Coarse-grain reconfigurable ASIC through multiplexer based switches

Karen Gettings, Marc Burke, Jeremy Muldavin, Michael Vai
2015 2015 IEEE High Performance Extreme Computing Conference (HPEC)  
A reconfigurable FFT ASIC was built as a proof of concept, and it successfully proved the switch implementation.  ...  We present an ASIC architecture with coarse grain reconfigurability, by using accelerators to improve performance over fine grain reconfigurable architectures.  ...  The incremental memory size per stage for a Radix-2 2 single delay feedback 16K FFT structure is located at the top of Figure 6 .  ... 
doi:10.1109/hpec.2015.7322438 dblp:conf/hpec/GettingsBMV15 fatcat:2xxivr7qfrdqfe5sbqhyp5hhga

A Novel Embedded Accelerator for Online Detection of Shrew DDoS Attacks

Hao Chen, Yu Chen
2008 2008 International Conference on Networking, Architecture, and Storage  
Taking advantages of powerful computing capability and software-like flexibility, an embedded accelerator using FPGA for PSD analysis has been proposed.  ...  As one type of stealthy and hard-to-detect attack, lowrate TCP-targeted DDoS attack can seriously throttle the throughput of normal TCP flows for a long time without being noticed.  ...  The well-known FFT algorithms are Radix-2N serial algorithms, which perform FFT operations on even number sequences. Radix-2 is the most compatible Radix-2N algorithm.  ... 
doi:10.1109/nas.2008.13 dblp:conf/iwnas/ChenC08 fatcat:76p6xljxrzaczijvbxy2bftgh4

Review of Parallel Polynomial Multiplier based on FFT using Indian Vedic Mathematics

Shilpa Jumde, R. N. Mandavgane, D. M. Khatri
2015 International Journal of Computer Applications  
These multipliers are used for multiplication of different polynomial numbers based on exponential type, power type, etc.  ...  In this paper, we have presented a review of parallel polynomial multiplier based on FFT using Indian Vedic mathematics.  ...  The radix-2 algorithm is a widely used algorithm for FFT processors, but it requires many complex multipliers.  ... 
doi:10.5120/19756-1379 fatcat:yhrgzw7qffhnjmjqqpr5kmqyye

On the performance and energy efficiency of FPGAs and GPUs for polyphase channelization

Vignesh Adhinarayanan, Thaddeus Koehn, Krzysztof Kepa, Wu-chun Feng, Peter Athanas
2014 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)  
Thus, in this paper, we present optimized polyphase channelizations for the FPGA and GPU, respectively, that must consider power and accuracy requirements in the context of a military application.  ...  However, the growing presence of low-power mobile GPUs holds much promise with improved flexibility for instant adaptation to different standards.  ...  FFT Design The FFT was implemented as a radix-2 decimation in frequency algorithm. This algorithm has several benefits to the channelizer.  ... 
doi:10.1109/reconfig.2014.7032542 dblp:conf/reconfig/AdhinarayananKK14 fatcat:d7kgljcutba2jbr24quix5l2aa

The FPGA-based continuous FFT tune measurement system for the LHC and its test at the CERN SPS

A. Boccardi, M. Gasior, O.R. Jones, K.K. Kasinski, R.J. Steinhagen
2007 2007 IEEE Particle Accelerator Conference (PAC)  
A base band tune (BBQ) measurement system has recently been developed at CERN based on a highsensitivity direct-diode detection technique followed by a high resolution FFT algorithm implemented in an FPGA  ...  The FPGA based digital processing allows the acquisition of continuous real-time spectra with 32-bit resolution, while a digital frequency synthesiser (DFS) can provide acquisition synchronised chirp excitation  ...  If the selected value is not a power of 4, as required for the radix-4 FFT algorithm, the data is automatically zero padded after the application of the window function.  ... 
doi:10.1109/pac.2007.4439982 fatcat:thmnjtgstngulm3zzikvacmffe

Fast Fourier Transform Implementation on FPGA Using Soft-Core Processor NIOS II
English

Poonam S. Isasare, Mahesh T. Kolte
2014 International Journal of Engineering Trends and Technoloy  
For loops with a recurrence, a speedup greater than 2 has been obtained; we show the basic C transformations that provide the best C2H results.  ...  In this work we use of the C2H Altera compiler for the automatic VHDL synthesis of FFT algorithm.  ...  There are some FFT algorithms have been developed, such as radix-2 algorithms, radix-2 m algorithms, Split-based FFT algorithm, Prime Factor algorithm, Winograd Fast Fourier Transform Algorithm (WFTA),  ... 
doi:10.14445/22315381/ijett-v10p278 fatcat:zulehnxfqfcqllrwnojgmeapvy

Design and Implementation of 1-D and 2-D Mixed Architecture FFT Processor in Heterogeneous Multi-core SoC based on FPGA

Duo-li Zhang, Lu Huang, Yu-kun Song, Gao-ming Du
2014 International Journal of Control and Automation  
As a result, relative acceleration ratio linear curve of 2-D FFT processor has a turning point appeared in point 2K. 2-D FFT processor operates slowly, but it's operating speed close to the theoretical  ...  As a result, we have implemented the mixed architecture FFT processor based on FPGA, and successfully applied it into the heterogeneous multi-core SoC. cycle is double compared to Radix-4 FFT algorithm  ...  Compared with design flow of general DSP or ASIC, designs based on FPGA have the advantages of flexibility, low power-consumption, short development time, low cost and high performance price ratio [11  ... 
doi:10.14257/ijca.2014.7.6.18 fatcat:d67bityrxjflxie6lxlkvpbvxe
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