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A logic sharing synthesis tool for mutually exclusive applications

Alp Kilic, Zied Marrakchi, Matthieu Tuna, Habib Mehrez
2012 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era  
Multiple Context ASIC (mASIC) is a circuit grouping a set of designs (applications) which operates at mutually exclusive times.  ...  In this paper we propose to take this particularity into account when we run logic synthesis. The idea is to maximize logic resources sharing between designs to reduce the total resulting area.  ...  Thus, we propose a logic sharing synthesis tool for mutually exclusive applications. The main idea is to achieve the best level of optimization in terms of area.  ... 
doi:10.1109/dtis.2012.6232984 fatcat:24vqtkmfkfhvvcflrqbmatkqkq

A Top-Down Optimization Methodology for Mutually Exclusive Applications

Alp Kilic, Zied Marrakchi, Habib Mehrez
2014 International Journal of Reconfigurable Computing  
Proliferation of mutually exclusive applications on circuits and the higher cost of silicon make the resource sharing more and more important.  ...  This paper proposes an efficient method to improve resource sharing between mutually exclusive applications with no dependence on the coding style.  ...  Applications are synthesized by taking into account the mutually exclusiveness of the applications. This gives to synthesis tool the freedom to share resources between applications.  ... 
doi:10.1155/2014/827613 fatcat:galfv7bzjrfltlc4tzpwqpr6l4

Hardware Reuse in Modern Application-Specific Processors and Accelerators

Alexandre S. Nery, Lech Jozwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, Felipe M.G. Franca
2011 2011 14th Euromicro Conference on Digital System Design  
It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective  ...  (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications.  ...  For instance, changing conditional statements, such as IF or CASE statements, may produce a different circuit [6] . The mutually exclusive forms are one of the bases for successful resource sharing.  ... 
doi:10.1109/dsd.2011.22 dblp:conf/dsd/NeryJLCNF11 fatcat:ic4zq3ct4jbwfjjgpa4wwtcq7e

Automatic communication synthesis with hardware sharing for design space exploration

Y Ando, S Shibata, S Honda, Hiroyuki Tomiyama, H Takada
2010 Proceedings of 2010 IEEE International Symposium on Circuits and Systems  
In this paper, we present a hardware sharing method for design space exploration of multiprocessor embedded systems.  ...  With the tool, designers only need to change the mapping information for hardware sharing. Designers therefore can easily explore wider design space with hardware sharing.  ...  AUTOMATIC COMMUNICATION SYNTHESIS WITH HARDWARE SHARING A. The Design Flow for Hardware Sharing It is assumed that a system consists of more than one application.  ... 
doi:10.1109/iscas.2010.5537849 dblp:conf/iscas/AndoSHTT10 fatcat:5gvyjozhsvbw7pbzcgtlhslosq

Resource sharing among mutually exclusive sum-of-product blocks for area reduction

Sabyasachi Das, Sunil P. Khatri
2008 ACM Transactions on Design Automation of Electronic Systems  
In this article, we introduce a novel, area-efficient architecture to share different SOP blocks which are used in a mutually exclusive manner.  ...  tool.  ...  To further reduce area, research techniques have been proposed, based on sharing, multiple, mutually exclusive datapath operations into a single block.  ... 
doi:10.1145/1367045.1367060 fatcat:3mckq4lsqnh57g2n5xhqufywd4

Efficient resource arbitration in reconfigurable computing environments

Iyad Ouaiss, Ranga Vemuri
2000 Proceedings of the conference on Design, automation and test in Europe - DATE '00  
In a multi-FPGA synthesis system, ideally the designer has only an abstract view of the board architecture.  ...  This abstract modeling of the underlying reconfigurable computer poses complex challenges to the synthesis and partitioning tools.  ...  Commercial logic and layout synthesis tools are used to complete logic synthesis, placement, and routing for each FPGA design segment.  ... 
doi:10.1145/343647.343856 fatcat:dtxelwyvkngxdgqriaapgtn5ru

Survey On Scheduling And Allocation In High Level Synthesis

M Chinnadurai
2012 International Journal of Computer Science & Engineering Survey  
This paper presents the detailed survey of scheduling and allocation techniques in the High Level Synthesis (HLS) presented in the research literature.  ...  It also presents the methodologies and techniques to improve the Speed, (silicon) Area and Power in High Level Synthesis, which are presented in the research literature.  ...  ACKNOWLEDGEMENTS We thank to the anonymous reviewers for their numerous insightful and constructive comments. Authors Dr.M.Joseph received his PhD degree in Computer Engineering from National  ... 
doi:10.5121/ijcses.2012.3503 fatcat:4uehu4ufxfbmdiozesymmzavpy

FMona: A Tool for Expressing Validation Techniques over Infinite State Systems [chapter]

J.-P. Bodeveix, M. Filali
2000 Lecture Notes in Computer Science  
In this paper, we present a generic tool, called FMona, for expressing validation methods. we illustrate its use through the expression of the abstraction technique and its application to infinite or parameterized  ...  The FMona tool is used to express the validation steps leading to synthesis of a finite abstract system;then SMV and/or Mona validate its properties.  ...  Application to the Bakery Mutual Exclusion Protocol The transition system of the Bakery mutual exclusion algorithm over two processes is described in FMona by the following code.  ... 
doi:10.1007/3-540-46419-0_15 fatcat:fftsaztvzjafvodmlmxwovkzcu

Synthesis of Multimode digital signal processing systems

C. Andriamisaina, E. Casseau, P. Coussy
2007 Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)  
In this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture.  ...  First results show the interest of the proposed synthesis flow.  ...  Multimode or multi-configuration cores are specifically designed for a set of time-wise mutually exclusive user-specified applications and target conventional hardware technologies.  ... 
doi:10.1109/ahs.2007.100 dblp:conf/ahs/AndriamisainaCC07 fatcat:ntcq2mbo2befraidwuq2ka3mpe

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

Oliver Schliebusch, A. Chattopadhyay, D. Kammler, G. Ascheid, R. Leupers, H. Meyr, Tim Kogel
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs).  ...  Gate-Level synthesis tools are not able to perform potential optimizations, as the computational complexity grows exponential with the size of the architecture.  ...  It builds up a list of sets. Each set contains all the paths, which can be shared. After the sets are built up for mutually exclusive nodes, the sharing is explored between them.  ... 
doi:10.1145/1120725.1120850 dblp:conf/aspdac/SchliebuschCKALMK05 fatcat:b224l5fkrzgudb4c22csvjfn44

Automated Multimode System Design For High Performance Dsp Applications

Emmanuel Casseau, Bertrand Le Gal
2009 Zenodo  
Timewise mutually exclusive relationship between the different modes is implemented by a conditional node statement to emphasis mutually exclusive branches. 3.  ...  However in most of SoC implementations, component utilization is low due to the high number of dedicated cores which are used in a timewise mutually exclusive way.  ...  Modes Synthesis constraints  ... 
doi:10.5281/zenodo.41401 fatcat:2y55reu4hfha3hqxctnv54s2vi

Fine-Grained Interconnect Synthesis

Alex Rodionov, David Biancolin, Jonathan Rose
2016 ACM Transactions on Reconfigurable Technology and Systems  
Using a design example, our tool generates interconnect that requires 69% fewer lines of specification code than a handwritten Verilog implementation, which is a 32% overall reduction for the entire application  ...  We also show a quantitative and qualitative advantages against an existing commercial interconnect synthesis tool, over which we achieve a 25% performance advantage and 15%/57% logic/memory area savings  ...  Mutually Exclusive Sharing In general many-to-one communication, there must exist some method for the interconnect to allow two or more inputs to share a common destination.  ... 
doi:10.1145/2892641 fatcat:vivno6yu7jgijelv5x5mqsrrvq

A New Approach and Tool in Verifying Asynchronous Circuits

Tin T. Nguyen, Khoi-Nguyen Le-Huu, Thang H. Bui, Anh-Vu Dinh-Duc
2013 REV Journal on Electronics and Communications  
Although there are some EDA tools for design and synthesis of asynchronous circuits, they are lack of methods for verifying the correctness of the produced circuits.  ...  In this work, we are about to propose a verification method and apply it in making a new version of the PAiD tool that can enable engineers to design, synthesize and verify asynchronous circuits.  ...  = 1) → EF(output = 1)) (3) Distributed Mutual Exclusion: The Distributed Mutual Exclusion (DME) is a well-known mutual exclusion problem in which some cyclic processes, called "masters", share a common  ... 
doi:10.21553/rev-jec.43 fatcat:h2aer34bj5cidpwrohheznmzda

RTL Scan Design for Skewed-Load At-Speed Test under Power Constraints

Ho Fai Ko, Nicola Nicolici
2006 Computer Design (ICCD '99), IEEE International Conference on  
third party test generation tools.  ...  Furthermore, as shown in experimental results, by constructing scan chains for the partitioned circuit at the RTL, area and performance penalty of the design-for-test hardware may be reduced.  ...  As mentioned above, it is difficult to find the mutually exclusive set of triggering and capturing FFs for a selected logic cone in a circuit.  ... 
doi:10.1109/iccd.2006.4380823 dblp:conf/iccd/KoN06 fatcat:pemvlteeo5azdd6qp47wny2z64

Inter-procedural resource sharing in High Level Synthesis through function proxies

Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi
2015 2015 25th International Conference on Field Programmable Logic and Applications (FPL)  
However, if two different callers invoke the same function, current HLS flows cannot share the instance of the module between the two callers, even if they invoke the function in a mutually exclusive way  ...  We show that module sharing through function proxies provides valuable area savings without significant impacts on the execution delays, and that our synthesis approach for function pointers enables dynamic  ...  Sharing at the level of FUs in fact, requires allocation of steering logic for each shared FU; sharing a function module instead, only requires allocation of steering logic for its inputs.  ... 
doi:10.1109/fpl.2015.7293958 dblp:conf/fpl/MinutoliCTF15 fatcat:w5p352xenvdmjmuekhi4zpoxuu
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