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A 65 mW fully integrated UHF-band CMMB tuner in 65 nm CMOS process

JunHua Liu, Chen Li, Long Chen, CongYin Shi, XuanKai Weng, YiXiao Wang, JiaYi Wang, Yu Liao, Le Ye, HuaiLin Liao, Ru Huang
2012 Science China Information Sciences  
The tuner is implemented in 65 nm CMOS process with low noise amplifier (LNA) matching network and phase locked loop (PLL) filter integrated on chip, occupying a chip area of 4.83 mm 2 .  ...  oscillator (VCO) covering 4.8-7.2 GHz is proposed for low power and small chip area.  ...  Ltd. for help in chip testing.  ... 
doi:10.1007/s11432-012-4708-2 fatcat:6erqr67gg5cv3dhkpeomczoruq

A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling

Mostafa G. Ahmed, Dongwook Kim, Romesh Kumar Nandwana, Ahmed Elkholy, Kadaba R. Lakshmikumar, Pavan Kumar Hanumolu
2021 IEEE Journal of Solid-State Circuits  
Fabricated in 65-nm CMOS process, the prototype RX achieves optical modulation amplitude (OMA) sensitivity of −11.6 dBm at 16 Gb/s with 0.7-pJ/bit efficiency.  ...  This article presents a low-power nonreturn-to-zero (NRZ) optical RX using a combination of a limited-bandwidth trans-impedance amplifier (TIA) and duobinary sampling to improve RX sensitivity at high  ...  ACKNOWLEDGMENT The authors would like to thank Vito Boccuzzi for his assistance in testing the receiver prototype. They would also like to thank Analog Devices for the partial financial support.  ... 
doi:10.1109/jssc.2021.3064248 fatcat:s5mkt5c4czde5jvsvpifcxavcq

Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC)

Makoto Nagata, Lucien J. Breems, Carlo Samori, Sven Mattisson, Pavan Kumar Hanumolu
2014 IEEE Journal of Solid-State Circuits  
The switched-mode operational amplifiers are proposed as a new class of feedback amplifier and leverage the faster switching speeds of nanoscale CMOS to realize high-linearity feedback amplifiers.  ...  Zhou et al. from Columbia University present, in the fifth paper, a blocker-resilient software-defined receiver in 65 nm CMOS with a low-noise active TX leakage cancellation scheme.  ... 
doi:10.1109/jssc.2014.2366411 fatcat:wityuhkaonfnzkbw52shpxo7i4

2019 Index IEEE Journal of Solid-State Circuits Vol. 54

2019 IEEE Journal of Solid-State Circuits  
., +, JSSC May 2019 1216-1227 A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS.  ...  for Low-Power Short-Range Wireless in 65-nm CMOS.  ... 
doi:10.1109/jssc.2019.2956675 fatcat:laiuae7dtragjijttgfatsldmu

A 200GHz downconverter in 90nm CMOS

Maarten Tytgat, Michiel Steyaert, Patrick Reynaert
2011 2011 Proceedings of the ESSCIRC (ESSCIRC)  
A 200 GHz downconverter in 90 nm standard CMOS is presented with a measured positive conversion gain of +6.6 dB and an IF bandwidth of 3 GHz for an LO power of −14.9 dBm.  ...  The conversion gain has a flatness of ±1.5 dB in an LO frequency range of 26 GHz. The IIP3 is −5.4 dBm. BPSK and QPSK data downconversion are demonstrated with a data rate of over 4 Gbit/s.  ...  TABLE I PERFORMANCE I SUMMARY AND COMPARISON TO OTHER WORK Reference [3] [4] [5] This work Process 0.1 µm GaAs mHEMT 65 nm CMOS 0.25 µm CMOS 90 nm CMOS RF (GHz ) 220 102 650 200 IF (MHz ) 2000 2000 0 to  ... 
doi:10.1109/esscirc.2011.6044951 dblp:conf/esscirc/TytgatSR11 fatcat:632vhs3o6jho3nkphsldov4tey

Design and Analysis of a Novel 24 GHz Up-Conversion Mixer with Improved Derivative Super-Position Linearizer Technique for 5G Applications

Abrar Siddique, Tahesin Samira Delwar, Prangyadarsini Behera, Manas Ranjan Biswal, Amir Haider, Jee-Youl Ryu
2021 Sensors  
A 24 GHz high linear, high-gain up-conversion mixer is realized for fifth-generation (5G) applications in the 65 nm CMOS process.  ...  The conversion gain of 4.1 dB at 24 GHz and 3.2 ± 0.9 dB, from 20 to 30 GHz is achieved in the designed mixer. Furthermore, a noise figure of 3.8 dB is noted at 24 GHz.  ...  Conclusions A 24 GHz up-conversion mixer using 65 nm CMOS technology is proposed for 5G automobile radar applications.  ... 
doi:10.3390/s21186118 pmid:34577325 pmcid:PMC8471453 fatcat:kgknjttzmbfvhkkre73vfg5u3y

Low Phase-Noise, 2.4 and 5.8 GHz Dual-Band Frequency Synthesizer with Class-C VCO and Bias-Controlled Charge Pump for RF Wireless Charging System in 180 nm CMOS Process

Jongwan Jo, David Kim, Arash Hejazi, YoungGun Pu, Yeonjae Jung, Hyungki Huh, Seokkee Kim, Joon-Mo Yoo, Kang-Yoon Lee
2022 Electronics  
Its FoM including the phase noise is −197 dB at 2.4 GHz and −202.8 GHz at 5.8 GHz, outperforming other PLLs designed in the 180 nm CMOS process.  ...  To improve the phase-noise characteristics under low power, a constant amplitude control class-C voltage-controlled oscillator (VCO) with a DC-DC converter, and a bias-controlled charge pump with a feedback  ...  Parameter [19] [20] [21] [22] [23] [23] This Work Technology 130 nm CMOS 65 nm CMOS 65 nm CMOS 130 nm CMOS 40 nm CMOS 40 nm CMOS 180 nm CMOS Supply Voltage (V) 1.5 1.2 1.2 1.3 1 1/0.8 1.8 Power Consumption  ... 
doi:10.3390/electronics11071118 fatcat:v7dtnio435cahpwfe6y454giyi

Design and analysis of high speed capacitive pipeline DACs

Quoc-Tai Duong, Jerzy Dąbrowski, Atila Alvandpour
2014 Analog Integrated Circuits and Signal Processing  
Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver.  ...  While it is possible to design a highly linear output driver with HD3 < -70 dB and HD2 < -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist  ...  In this paper we present design of a simple pipeline SC DAC with a highly linear output driver using 65 nm CMOS technology. The main objective is achieving maximum data rate in this architecture.  ... 
doi:10.1007/s10470-014-0350-9 fatcat:zqkr7ppwm5cgdlkkx5bwyrgkxi

Pulse-Width Modulated CMOS Power Amplifiers

Jeffrey Walling, David Allstot
2011 IEEE Microwave Magazine  
The power amplifi er (PA) is currently the gating element to the realization of a full complimentary metal-oxide-semiconductor (CMOS) RF-SOC solution due to its relatively poor performance when compared  ...  CMOS suffers in comparison for two main reasons: 1) Scaling of  ...  Fabricated in a 65-nm low-leakage CMOS process with eight layers of metallization, it occupies 1.6 mm 3 1.3 mm.  ... 
doi:10.1109/mmm.2010.939304 fatcat:l7wouwbmgbfsvoktnfvujbeiu4

An inductorless 3–5 GHz band-pass filter with tunable center frequency in 90 nm CMOS

Tuan Anh Vu, Shanthi Sudalaiyandi, Hakon A. Hjortland, Oivind Nass, Tor Sverre Lande
2013 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)  
The front-end consists of an antenna, a low noise amplifier, a band-pass filter, a downconversion quadrature mixer, a low-pass filter, a differential-to-single-ended converter and a continuous-time quantizer  ...  With traditional clock driven circuit solutions, we need a clock rate of more than 30 GHz, which is not easy in standard technology.  ...  Acknowledgements This thesis has been submitted to the Faculty of Mathematics and Natural Sciences at the University of Oslo as a part of the requirements for the degree of Philosophiae Doctor in informatics  ... 
doi:10.1109/iscas.2013.6572088 dblp:conf/iscas/VuSHNL13 fatcat:qsh4hcdyobh2tj33ga5t3zdlqi

RFIC 2020 Program

2020 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)  
Abstract: This paper reports on the design of a 60 GHz low-noise amplifier (LNA) with a linear and power efficient gain tuning mechanism in a 65 nm CMOS process.  ...  The chip was fabricated in TSMC's 65 nm CMOS, and it occupies an area of 1.6 mm 2 .  ...  A modulator that provides outphasing signals to synthesize RF-PWM without a narrow pulse-width limitation is proposed. The Cartesian transmitter is implemented in a 65-nm CMOS process.  ... 
doi:10.1109/rfic49505.2020.9218389 fatcat:fqkpw3oau5gzpoi3gscgb7kwhi

A 2.4/5.8 GHz 10 μW wake-up receiver with −65/−50 dBm sensitivity using direct active rf detection

Kuang-Wei Cheng, Xin Liu, Minkyu Je
2012 2012 IEEE Asian Solid State Circuits Conference (A-SSCC)  
It achieves a sensitivity of -65 dBm for data rate of 100 kbps, operating in 2.4 GHz ISM band with only 10 µW.  ...  This complete receiver contains an RF detector, IF amplifiers, and a continuous-time ΣΔ ADC to provide inherent anti-alias filtering, which simplifies the overall design in 0.18-µm CMOS process.  ...  Sensitivity (dBm) -50 -65 -72 -65 -45 -71 Carrier Frequency (GHz) 5.8 2.4 2 2.4 5.8 0.868 Data Rate (kHz) 100 100 100 14 100 Supply Voltage (V) 0.5 0.5 0.5 3.3 1 CMOS Process (nm) 180 90 90 130 130  ... 
doi:10.1109/ipec.2012.6522694 fatcat:wuaw45x2pngqfhoitjeumvaztm

Field-Programmable LNAs With Interferer-Reflecting Loop for Input Linearity Enhancement

Jianxun Zhu, Harish Krishnaswamy, Peter R. Kinget
2015 IEEE Journal of Solid-State Circuits  
Index Terms-Bondwire filter, CMOS, feedback loop, field programmable, high linearity, interferer reflection, LNA, LNA linearization, low-noise amplifiers, low power, N-path filter, radio-frequency integrated  ...  and the LNA input linearity is improved. 65 nm CMOS chip prototypes have been implemented with on-chip LC, bondwire LC or N-path notch filters.  ...  William Chappell (DARPA) and Yang Xu (Columbia University) for technical discussions, and Bob Melville for assistance in measurements.  ... 
doi:10.1109/jssc.2014.2364835 fatcat:t5lpulqpyvamdntsdd6csmbsle

Nanoscale CMOS Transceiver Design in the 90–170-GHz Range

E. Laskin, M. Khanpour, S.T. Nicolson, A. Tomkins, P. Garcia, A. Cathelin, D. Belot, S.P. Voinigescu
2009 IEEE transactions on microwave theory and techniques  
A Doppler transceiver and two receivers fabricated in a 65-nm GPLP CMOS technology are described, along with a single pole, double throw antenna switch with better than 5-dB insertion loss and 25-dB isolation  ...  Unique nanoscale CMOS issues related to millimeter-wave circuit design in the 65-nm node and beyond are addressed with an emphasis on transistor and top-level layout issues, low-voltage circuit topologies  ...  Access to the 94-GHz vector network analyzer in the ECTI facility, University of Toronto, is also acknowledged. Finally, the authors also thank J.  ... 
doi:10.1109/tmtt.2009.2034071 fatcat:5sc35gd5mvb6ffjtoz6dqhdv7y

A Transformer Noise-Canceling Ultra-Wideband CMOS Low-Noise Amplifier

Takao KIHARA, Toshimasa MATSUOKA, Kenji TANIGUCHI
2010 IEICE transactions on electronics  
Previously reported wideband CMOS low-noise amplifiers (LNAs) have difficulty in achieving both wideband input impedance matching and low noise performance at low power consumption and low supply voltage  ...  The LNA designed for ultra-wideband (UWB) applications is implemented in a 90 nm digital CMOS process.  ...  In addition, this study was financially supported by a grant to the Osaka University Global COE Program, "Center for Electronic Devices Innovation" from the Ministry of Education, Culture, Sports, Science  ... 
doi:10.1587/transele.e93.c.187 fatcat:qqx6zezqdneplhyfp2jhnonch4
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