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Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

Zhi Li, Jingweijia Tan, Xin Fu
2013 International Symposium on Quality Electronic Design (ISQED)  
CMOS-based registers are still used for threads requiring normal execution speed.  ...  In this study, we propose the hybrid CMOS-TFET based register files.  ...  EPS-0903806 and matching support from the State of Kansas through the Kansas Board of Regents.  ... 
doi:10.1109/isqed.2013.6523598 dblp:conf/isqed/LiTF13 fatcat:467p5zhwdvaw7pleeuawo6wr6a

Hybrid-cell register files design for improving NBTI reliability

N. Gong, S. Jiang, J. Wang, B. Aravamudhan, K. Sekar, R. Sridhar
2012 Microelectronics and reliability  
In this paper, a hybrid-cell RF design technique is proposed to achieve high reliability by storing the most vulnerable bits in robust 8T cells and other bits in conventional 6T cells.  ...  In modern processors, register files (RF) suffers from NBTI induced degradation with technology scaling.  ...  These benchmarks are compiled for the Alpha ISA and use the reference input set.  ... 
doi:10.1016/j.microrel.2012.06.045 fatcat:7sd5xhtnfbbbfnakc5iltrbq6y

Adapting the columns of storage components for lower static energy dissipation

Mehmet Burak Aykenar, Muhammet Ozgur, Osman Seckin Simsek, Oguz Ergin
2013 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)  
Our simulations reveal that when our technique is used in the register file of the processor, the leakage energy dissipation decreases by 39% and the total energy dissipation by 14% with an area overhead  ...  SRAM arrays are used especially in memory structures inside the processor.  ...  Banking and clock gating strategies are used to reduce the power dissipation of the register file.  ... 
doi:10.1109/vlsi-soc.2013.6673279 dblp:conf/vlsi/AykenarOSE13 fatcat:ksvejd7ymvgpzohkehiphmk73u

Is overlay error more important than interconnect variations in double patterning?

Kwangok Jeong, Andrew B. Kahng, Rasit O. Topaloglu
2009 Proceedings of the 11th international workshop on System level interconnect prediction - SLIP '09  
ORION [29] was amongst the first NoC power models released, and has since been fairly widely used for early-stage power estimation of NoCs.  ...  A case study with these power models plugged within the COSI-OCC NoC design space exploration tool [23] confirms the need for, and value of, accurate early-stage NoC power estimation.  ...  Sriram Vangal and Dr. Anthony Chun of Intel Corporation for providing us the Intel 80-core Teraflops and the Intel SCC power estimates, Dr.  ... 
doi:10.1145/1572471.1572474 dblp:conf/slip/JeongKT09 fatcat:s4wnrttfdffjlmwbqrptbb7xke

Design of Hybrid Second-Level Caches

Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro Lopez, Jose Duato
2015 IEEE transactions on computers  
Additionally, it was also supported by the Intel Early Career Honor Programme Award and the Intel Doctoral Student Honor Programme Award.  ...  ACKNOWLEDGMENTS This work was supported by the Spanish Ministerio de Economía y Competitividad (MINECO) and FEDER funds under Grant TIN2012-38341-C04-01.  ...  In [30] , Wang et al. describe a low-cost adaptive block placement for hybrid MRAM/SRAM L2 caches referred to as Adaptive Placement and Migration (APM).  ... 
doi:10.1109/tc.2014.2346185 fatcat:4kegsyg7lzc53pmaagy7jcwbu4

Enabling GPGPU Low-Level Hardware Explorations with MIAOW

Raghuraman Balasubramanian, Pradip Valathol, Karthikeyan Sankaralingam, Vinay Gangadhar, Ziliang Guo, Chen-Han Ho, Cherin Joseph, Jaikrishnan Menon, Mario Paulo Drumond, Robin Paul, Sharath Prasad
2015 ACM Transactions on Architecture and Code Optimization (TACO)  
While useful for modeling first-order effects, these tools do not provide a detailed view of GPU microarchitecture and physical design.  ...  Further, as GPGPU research evolves, design ideas and modifications demand detailed estimates of impact on overall area and power.  ...  For those interested in performing power analysis using a specific technology process for the register elements (including SRAM based), many register compilers, hard macros, and modeling tools like CACTI  ... 
doi:10.1145/2764908 fatcat:utj6prgm2zcctlb36ikgejny2e

AnySP

Mark Woh, Sangwon Seo, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztian Flautner
2009 SIGARCH Computer Architecture News  
AnySP uses a co-design approach where the next generation wireless signal processing and high-definition video algorithms are analyzed to create a domain specific programmable architecture.  ...  To overcome these challenges, this paper proposes an example architecture, referred to as AnySP , for the next generation mobile signal processing.  ...  ACKNOWLEDGEMENTS We thank Ron Dreslinski for his help in organizing and editing this paper. We also thank the anonymous referees for their useful comments and suggestions.  ... 
doi:10.1145/1555815.1555773 fatcat:m3psv47xdbgvjcvfu2gzlqe5eu

AnySP: Anytime Anywhere Anyway Signal Processing

Mark Woh, Sangwon Seo, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztian Flautner
2010 IEEE Micro  
AnySP uses a co-design approach where the next generation wireless signal processing and high-definition video algorithms are analyzed to create a domain specific programmable architecture.  ...  To overcome these challenges, this paper proposes an example architecture, referred to as AnySP , for the next generation mobile signal processing.  ...  ACKNOWLEDGEMENTS We thank Ron Dreslinski for his help in organizing and editing this paper. We also thank the anonymous referees for their useful comments and suggestions.  ... 
doi:10.1109/mm.2010.8 fatcat:euz67s3x7bfe5e5cx7qkxbplva

AnySP

Mark Woh, Sangwon Seo, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztian Flautner
2009 Proceedings of the 36th annual international symposium on Computer architecture - ISCA '09  
AnySP uses a co-design approach where the next generation wireless signal processing and high-definition video algorithms are analyzed to create a domain specific programmable architecture.  ...  To overcome these challenges, this paper proposes an example architecture, referred to as AnySP , for the next generation mobile signal processing.  ...  ACKNOWLEDGEMENTS We thank Ron Dreslinski for his help in organizing and editing this paper. We also thank the anonymous referees for their useful comments and suggestions.  ... 
doi:10.1145/1555754.1555773 dblp:conf/isca/WohSMMCF09 fatcat:vixlauv7u5c4pplb7v2tsfufv4

Transforming a linear algebra core to an FFT accelerator

Ardavan Pedram, John McCalpin, Andreas Gerstlauer
2013 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors  
We examine design trade-offs between efficiency, specialization and flexibility, and their effects both on the core and memory hierarchy for a unified design as compared to dedicated accelerators for each  ...  Results show that the proposed hybrid FFT/Linear Algebra core can achieve 26.6 GFLOPS/S with a power efficiency of 40 GFLOPS/W, which is up to 100× and 40× more energy efficient than cutting-edge CPUs  ...  Any opinions, findings and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation (NSF).  ... 
doi:10.1109/asap.2013.6567572 dblp:conf/asap/PedramMG13 fatcat:g5c26k3qr5el7h5ojwtctouyfa

Fault tolerant electronic system design

Boyang Du, Luca Sterpone
2017 2017 IEEE International Test Conference (ITC)  
This work mainly focuses on online test for detecting CFEs in the first part, a hybrid solution is discussed afterwards.  ...  them are difficult to handle, such as the faults affecting ii the registers used in the pipeline of the processor.  ...  Luca Sterpone and Prof. Matteo Sonza Reorda for providing  ... 
doi:10.1109/test.2017.8242080 dblp:conf/itc/DuS17 fatcat:fyonsldknjcutb5p2hiq6brcd4

A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores

Ardavan Pedram, John D. McCalpin, Andreas Gerstlauer
2014 Journal of Signal Processing Systems  
Starting with a highly efficient hybrid linear algebra/FFT core, we co-design the on-chip memory hierarchy, on-chip interconnect, and FFT algorithms for a multicore FFT processor.  ...  The result is an architecture that can effectively use up to 16 hybrid cores for transform sizes that can be contained in on-chip SRAM.  ...  Acknowledgements Authors wish to thank John Brunhaver for providing synthesis results for the raw components of the Transposer.  ... 
doi:10.1007/s11265-014-0896-x fatcat:ce5vw2a4dne5bmlkwbjuxdr75q

2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26

2018 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
., see 2723-2736 , VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems; TVLSI Feb. 2018 262-271 Hsieh, Y., see Tsai, Y., TVLSI May 2018 945-957  ...  Hsu, K., Chen, Y., Lee, Y., and Chang, S., Contactless Testing for Prebond Interposers; TVLSI June 2018 1005-1014 Hsu, Y., see Liu, Z., 1565-1574 Hu, J., see Wang, Y., TVLSI May 2018 805-817 Hu, J  ...  ., +, TVLSI Nov. 2018 2230-2240 Integrated circuit reliability In Situ and In-Field Technique for Monitoring and Decelerating NBTI in 6T-SRAM Register Files.  ... 
doi:10.1109/tvlsi.2019.2892312 fatcat:rxiz5duc6jhdzjo4ybcxdajtbq

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

I. Herrera-Alzu, M. Lopez-Vallejo
2013 IEEE Transactions on Nuclear Science  
This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers.  ...  This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications.  ...  Future work is outlined in the research of novel design methodologies and architectures for reliability-aware and power-aware configuration memory scrubbers for SRAM-based FPGAs.  ... 
doi:10.1109/tns.2012.2231881 fatcat:y34el2up7nhvzbrhecksrkogri

An energy-efficient adaptive hybrid cache

Jason Cong, Karthik Gururaj, Hui Huang, Chunyue Liu, Glenn Reinman, Yi Zou
2011 IEEE/ACM International Symposium on Low Power Electronics and Design  
However, existing hybrid caches provide a flexible partitioning of cache and SPM without considering adaptation to the run-time cache behavior.  ...  By reconfiguring part of the cache as softwaremanaged scratchpad memory (SPM), hybrid caches manage to handle both unknown and predictable memory access patterns.  ...  The authors thank Mishali Naik and Jiajun Zhang for helpful discussions and assistance in experiments, and the anonymous reviewers for their useful comments on this work.  ... 
doi:10.1109/islped.2011.5993609 fatcat:dtowx4g535cafcsqaapkwqt3wa
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