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A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC

Muhammad Nadeem, Stephan Wong, Georgi Kuzmanov, Ahsan Shabbir
2009 2009 IEEE/ACM/IFIP 7th Workshop on Embedded Systems for Real-Time Multimedia  
In this paper, we present a high-throughput, areaefficient, hardware accelerator for the deblocking filter in H.264/AVC video compression standard.  ...  high throughput at one hand and less area in terms of equivalent gates count on the other, when compared with existing state-ofthe-art hardware accelerators in the literature.  ...  CONCLUSIONS This paper presents a high-throughput, area-efficient, hardware accelerator for the deblocking filter in H.264/AVC and proposes a decomposition of the filter kernels, which reduces the number  ... 
doi:10.1109/estmed.2009.5336814 dblp:conf/estimedia/NadeemWKS09 fatcat:jazon3dpknaqdlzojajg72y3rq

Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding

Ke Xu, Tsu-Ming Liu, Jiun-In Guo, Chiu-Sing Choy
2009 Journal of Signal Processing Systems  
This paper presents methods for efficient optimization of ASIC implementation for H.264/AVC video decoding. A systematic approach in optimization is presented in a top-down flow.  ...  Tradeoffs among Power, Throughput, and Area (PTA) at both system level and block level are studied and balanced. The system architecture is first evaluated.  ...  Deblocking Filter As compared to the filters used in previous video standards such as MPEG-2 or H.263, the in-loop deblocking filter of H.264/AVC is much more complex due to higher adaptability of filter  ... 
doi:10.1007/s11265-009-0408-6 fatcat:dhvbpcut5bgonhbe5y2dbetc5m

Hardware architecture design of an H.264/AVC video codec

Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
H.264/AVC is the latest video coding standard.  ...  Due to the complex, sequential, and highly data-depended characteristics of all essential algorithms in H.264/AVC, not only the pipeline structure but also efficient memory hierarchy is required.  ...  As for H.264/AVC encoder, up to 3600 GIPS and 5570 GBPS are required for HDTV720P (1280×720, 30fps) specification. For real-time applications, accelerating by the dedicated hardware is a must.  ... 
doi:10.1145/1118299.1118473 fatcat:i7xscbbjvbew3jlmjda3cwhqky

Algorithms and DSP implementation of H.264/AVC

Hung-Chih Lin, Yu-Jen Wang, Kai-Ting Cheng, Shang-Yu Yeh, Wei-Nien Chen, Chia-Yang Tsai, Tian-Sheuan Chang, Hsueh-Ming Hang
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
In addition, in order to port the H.264/AVC codec to DSP, we also outline the basic principles of DSP code optimization.  ...  This survey paper intends to provide a comprehensive coverage of the techniques that are pertinent to the processor-based implementation of H.264/AVC video codec, particularly on DSP.  ...  Conclusions H.264/AVC is an efficient video compression scheme but this codec, particularly the encoder, has a very high computational complexity.  ... 
doi:10.1145/1118299.1118472 fatcat:dlecsrq3svbbnepvmg653xn6ci

Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

Tung-Chien Chen, Shao-Yi Chien, Yu-Wen Huang, Chen-Han Tsai, Ching-Yeh Chen, To-Wei Chen, Liang-Gee Chen
2006 IEEE transactions on circuits and systems for video technology (Print)  
In this paper, we describe our techniques to design the H.264/AVC video encoder for HDTV applications.  ...  With these techniques, the prototype chip of the efficient H.264/AVC encoder is implemented with 922.8 K logic gates and 34.72-KB SRAM at 108-MHz operation frequency.  ...  For real-time applications, the acceleration by a dedicated hardware is a must. However, it is difficult to design the architecture for the H.264/AVC hardwired encoder.  ... 
doi:10.1109/tcsvt.2006.873163 fatcat:xkacmieygfabtnysizpqozmeva

A 135 MHz 542 k Gates High Throughput H.264/AVC Scalable High Profile Decoder

Gwo-Long Li, Yu-Chen Chen, Yuan-Hsin Liao, Po-Yuan Hsu, Meng-Hsun Wen, Tian-Sheuan Chang
2012 IEEE transactions on circuits and systems for video technology (Print)  
This paper presents an H.264/AVC scalable high profile decoder realization with several optimization techniques to provide high throughput video decoding.  ...  Finally, the proposed H.264/AVC scalable high profile decoder design is implemented with 90 nm CMOS technology and it costs 542 k gate count and 39.66 Kbytes on-chip memory while is capable to decode 60  ...  A 135 MHz 542 k Gates High Throughput H.264/AVC Scalable High Profile Decoder H.264/AVC called scalable video coding (SVC) [1] has been standardized recently which can encode the video sources with diverse  ... 
doi:10.1109/tcsvt.2011.2171213 fatcat:d5pxven3wnbptny32jmijodflm

VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC

Yi-Hau Chen, Tung-Chien Chen, Shao-Yi Chien, Yu-Wen Huang, Liang-Gee Chen
2008 Journal of Signal Processing Systems  
Acceleration by dedicated hardware is a must for real-time applications.  ...  The H.264/AVC Fractional Motion Estimation (FME) with rate-distortion constrained mode decision can improve the rate-distortion efficiency by 2-6 dB in peak signal-to-noise ratio.  ...  Due to the huge computation complexity and sequential issues in the high complexity mode of H.264/AVC, it is less suitable for real-time applications.  ... 
doi:10.1007/s11265-008-0213-7 fatcat:vj523iqj3rfijogrnpjkgvjdiq

Performance evaluation of H.264/AVC decoding and visualization using the GPU

Bart Pieters, Dieter Van Rijsselbergen, Wesley De Neve, Rik Van de Walle, Andrew G. Tescher
2007 Applications of Digital Image Processing XXX  
The coding efficiency of the H.264/AVC standard makes the decoding process computationally demanding. This has limited the availability of cost-effective, high-performance solutions.  ...  As an example, real-time playback of high-definition video (1080p) was achieved with our Direct3D and CUDA-based H.264/AVC renderers.  ...  ACKNOWLEDGEMENTS The research as described in this paper was funded by Ghent University, the Interdisciplinary Institute for Broadband Technology (IBBT), the Institute for the Promotion of Innovation by  ... 
doi:10.1117/12.733151 fatcat:hkt6kqirare3nc3hhje7k7fdd4

VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding

Huang-Chih Kuo, Youn-Long Lin
2013 IPSJ Transactions on System LSI Design Methodology  
We present a VLSI design for H.264/AVC intra-frame encoder.  ...  It also delivers the same video quality as the H.264/AVC reference software. We suggest a figure of merit called Design Efficiency for fair comparison of different works.  ...  We present an efficient H.264/AVC intra-frame encoder.  ... 
doi:10.2197/ipsjtsldm.6.76 fatcat:l43vwym2mndnhhbfxrpfdhuavm

A Multiple-Window Video Embedding Transcoder Based on H.264/AVC Standard

Chih-Hung Li, Chung-Neng Wang, Tihao Chiang
2007 EURASIP Journal on Advances in Signal Processing  
This paper proposes a low-complexity multiple-window video embedding transcoder (MW-VET) based on H.264/AVC standard for various applications that require video embedding services including picture-in-picture  ...  It improves the transcoding speed with three block level adaptive techniques including slice group based transcoding (SGT), reduced frame memory transcoder (RFMT), and syntax level bypassing (SLB).  ...  ACKNOWLEDGMENT This work was supported in part by the National Science Council of the Republic of China, under Grant NSC 95-2221-E009-074-MY3.  ... 
doi:10.1155/2007/13790 fatcat:zeeybxkapnhxhg7csylas56rrq

A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder

Yuan-Hsin Liao, Gwo-Long Li, Tian-Sheuan Chang
2012 IEEE transactions on circuits and systems for video technology (Print)  
In this paper, a high throughput context-based adaptive binary arithmetic coding decoder design is proposed. This decoder employs a syntax element prediction method to solve pipeline hazard problems.  ...  to support H.264/AVC level 5.1 real-time decoding.  ...  As a result, a hardware accelerator for entropy decoding is indispensable for a real-time HD H.264/AVC video decoder.  ... 
doi:10.1109/tcsvt.2011.2160752 fatcat:3fmrj3azp5aancq52zsz4fjq4m

A 1080p H.264/AVC Baseline Residual Encoder for a Fine-Grained Many-Core System

Zhibin Xiao, Bevan M. Baas
2011 IEEE transactions on circuits and systems for video technology (Print)  
This paper presents a baseline residual encoder for H.264/AVC on a programmable fine-grained many-core processing array that utilizes no application-specific hardware.  ...  Compared to a heterogeneous single instruction, multiple data architecture customized for H.264, the presented design has 2.8-3.6 times greater throughput, 4.5-5.9 times higher area efficiency, and similar  ...  Some other hybrid architectures use a hardware software codesign approach to speedup only complex tasks in H.264/AVC encoding such as motion estimation and context adaptive binary arithmetic coding [10  ... 
doi:10.1109/tcsvt.2011.2133290 fatcat:lgt6oyaqcjfpremcrkvmsgxa7i

Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder

Yu-Wen Huang, Bing-Yu Hsieh, Tung-Chien Chen, Liang-Gee Chen
2005 IEEE transactions on circuits and systems for video technology (Print)  
The other solution is a hardware accelerator targeted at high-end applications.  ...  A low cost general purpose processor cannot process these operations in real time. In this paper, we proposed two solutions for platform-based design of H.264/AVC intra frame coder.  ...  JPEG2000 eliminates the block artifact by adopting DWT while H.264/AVC achieves it by deblocking.  ... 
doi:10.1109/tcsvt.2004.842620 fatcat:fc3mcqqjz5huvmu7b5qoevwm7u

Adaptive Low-Power Architectures for Embedded Multimedia Systems [chapter]

Muhammad Shafique, Jörg Henkel
2011 Hardware/Software Architectures for Low-Power Embedded Multimedia Systems  
study of H.264/AVC video codec.  ...  In this dissertation, we target high-performance in terms of low-power, highthroughput, area-efficient, and flexible digital signal processing for batterypowered multimedia embedded systems, with a case  ...  Subsequently, for real-time video processing applications, we have presented a high-throughput, area-efficient, hardware accelerator for the deblocking filter in H.264/AVC.  ... 
doi:10.1007/978-1-4419-9692-3_3 fatcat:hfcxk5zklfdodffl4hwvgurz6u

Algorithm analysis and architecture design for HDTV applications

Tung-Chien Chen, Hung-Chi Fang, Chung-Jr Lian, Chen-Han Tsai, Yu-Wen Huang, To-Wei Chen, Ching-Yeh Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen
2006 IEEE Circuits & Devices  
T he new H.264/AVC coding standard significantly outperforms previous video coding standards with many new coding tools. However, the high performance comes at a price.  ...  The efficient H.264/AVC video coding system is achieved by combining these techniques.  ...  Adaptive filter taps and two-filter direction also must be supported for in-loop deblocking filters.  ... 
doi:10.1109/mcd.2006.1657846 fatcat:w7ir2pibtzh4vjv54i26co7raa
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