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Hardware architecture design of an H.264/AVC video codec

Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
This paper describes the design methodology for H.264/AVC video codec. The system architecture and scheduling will be addressed.  ...  H.264/AVC is the latest video coding standard.  ...  H.264/AVC DECODING SYSTEM In this section, a methodology to determine a suitable pipelining structure of a H.264/AVC decoder is presented. The target resolution is HDTV1024P 30fps videos.  ... 
doi:10.1145/1118299.1118473 fatcat:i7xscbbjvbew3jlmjda3cwhqky

Multifactor Authentication Scheme for Wireless H.264/AVC Video Streaming

C. Chandrasekar, Manuprasad V.
2016 International Journal of Computer Applications  
The experimental results on H.264/AVC video streaming confirm the effectiveness of this VAP and demonstrates that comparison with other video authentication schemes.  ...  Such video coding standards such as H.261, CCIR 723, MPEG-1 and MPEG-2 H.264/AVC has several challenges in inventing effective authentication scheme.  ...  We enhance the existing joint source-channel adaptive scheme method along with multi factor authentication scheme which makes suitable for the H.264/AVC video streaming.  ... 
doi:10.5120/ijca2016908448 fatcat:7gjcqp4cyncf5avmqtg3zlnszi

Architecture Design of The Hardware H.264/AVC Video Decoder

Mikołaj Roszkowski, Andrzej Abramowski, Michał Wieczorek, Grzegorz Pastuszak
2010 International Journal of Electronics and Telecommunications  
Architecture Design of The Hardware H.264/AVC Video Decoder The need for real-time video compression systems requires a particular design methodology to achieve high troughput devices.  ...  The paper describes the architecture of the H.264/AVC decoder able to support SDTV and HDTV resolutions.  ...  This paper presents the architecture of a H.264/AVC decoder designed to support a real time decoding of H.264/AVC High Profile (except for MBAFF processing mode) sequences with video resolutions up to  ... 
doi:10.2478/v10177-010-0039-7 fatcat:nhctikbqmngk3atpcrzzejqalu

H.264/AVC Video Encoder Realization and Acceleration on TI DM642 DSP [chapter]

Daw-Tung Lin, Chung-Yu Yang
2009 Lecture Notes in Computer Science  
This work develops and optimizes H.264/AVC video encoder on the TM320DM642 DSP platform.  ...  Experimental results reveal that the optimized H.264 video encoder retains satisfactory quality with very low degradation.  ...  Introduction H.264/AVC video coding technology provides better bit rate saving and high flexibility of use in a broad variety of domains video compression standards.  ... 
doi:10.1007/978-3-540-92957-4_79 fatcat:mjjyymo6znbdhe7lgnon7l7pqm

Region-of-Interest based Preprocessing for H.264/AVC Encoding

Minghui WANG, Tianruo ZHANG, Chen LIU, Satoshi GOTO
2010 The Journal of the Institute of Image Electronics Engineers of Japan  
〈Summary〉 H.264/AVC achieves low bit-rate video stream which meets the requirement of video communication. The problem of H.264/AVC is the large computation burden.  ...  This design is decoding-friendly. Experimental result shows a large amount computation is saved and the subjective visual quality is kept or even improved.  ...  Complexity background makes the performance worse. Paper : Region-of-Interest based Preprocessing for H.264/AVC Encoding to reduce the computation burden for the conventional H.264 encoder.  ... 
doi:10.11371/iieej.39.682 fatcat:36zylhlqnre3jcaehwhqg3ad7m

Optimizing coarse-grain reconfigurable hardware utilization through multiprocessing: an H.264/AVC decoder example

Andreas Kanstein, Sebastian López Suárez, Bjorn De Sutter, Valentín de Armas Sosa, Kamran Eshraghian, Félix B. Tobajas
2007 VLSI Circuits and Systems III  
This paper discusses the architecture and an exploration into how to potentially partition a given array for executing an H.264/AVC baseline decoder.  ...  Coarse-grained reconfigurable architectures offer high execution acceleration for code which has high instruction-level parallelism (ILP), typically for large kernels in DSP applications.  ...  EXAMPLE: H.264/AVC DECODER The ITU-T H.264, also known as MPEG-4 (Part 10) Advanced Video Coding and therefore also called H.264/AVC in short, represents the latest evolution of video codecs [11] .  ... 
doi:10.1117/12.722077 fatcat:kg5dvj7p7zerlmckn5uacazsli

Effectiveness of Crypto-Transcoding for H.264/AVC and HEVC Video Bit-streams [article]

Rizwan A. Shah, Mamoona N. Asghar, Saima Abdullah, Martin Fleury, and Neelam Gohar
2019 arXiv   pre-print
Specifically, the paper outlines a joint crypto-transcoding scheme for secure transrating of a video bitstream.  ...  The scheme is suited to both recent standardized codecs, namely H.264/Advanced Video Coding (AVC) and High Efficiency Video Coding (HEVC).  ...  Low High in scheme 1. Low in scheme 2 but produced error drift after transcoding Low for H.264/AVC, medium for HEVC due to video encoding time  ... 
arXiv:1902.06990v1 fatcat:ar4oivsygzcp3bc3iq6h5mj7tm

VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding

Huang-Chih Kuo, Youn-Long Lin
2013 IPSJ Transactions on System LSI Design Methodology  
We present a VLSI design for H.264/AVC intra-frame encoder.  ...  It also delivers the same video quality as the H.264/AVC reference software. We suggest a figure of merit called Design Efficiency for fair comparison of different works.  ...  Moreover, the H.264/AVC standard defines a high profile to support super high definition video.  ... 
doi:10.2197/ipsjtsldm.6.76 fatcat:l43vwym2mndnhhbfxrpfdhuavm

Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems

Tiago Dias, Nuno Roma, Leonel Sousa
2010 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)  
This paper presents a multi-core H.264/AVC encoder suitable for implementations in small and medium complexity embedded systems.  ...  Experimental results obtained with the implementation in a Virtex4 FPGA of an H.264/AVC encoder using an ASIP IP core as a ME hardware accelerator have proven the advantages of this methodology.  ...  INTRODUCTION The H.264/AVC standard is nowadays the de-facto standard for video applications, due to its high coding efficiency and flexibility [1] .  ... 
doi:10.1109/dasip.2010.5706271 dblp:conf/dasip/DiasRS10 fatcat:cumzo6nt4bad3c6qbwwntyq5im

A Multiple-Window Video Embedding Transcoder Based on H.264/AVC Standard

Chih-Hung Li, Chung-Neng Wang, Tihao Chiang
2007 EURASIP Journal on Advances in Signal Processing  
This paper proposes a low-complexity multiple-window video embedding transcoder (MW-VET) based on H.264/AVC standard for various applications that require video embedding services including picture-in-picture  ...  that, as compared to the cascaded pixel domain transcoder (CPDT) with the highest complexity, our MW-VET can significantly reduce the processing complexity by 25 times and retain the rate-distortion performance  ...  However, this is not the case for the H.264/AVC standard.  ... 
doi:10.1155/2007/13790 fatcat:zeeybxkapnhxhg7csylas56rrq

Reducing the Complexity of a Multiview H.264/AVC and HEVC Hybrid Architecture

A. J. Díaz-Honrubia, J. De Praeter, J. L. Martínez, P. Cuenca, G. Van Wallendael
2016 Journal of Signal Processing Systems  
Thus, a multiview H.264/Advance Video Coding (AVC) and High Efficiency Video Coding (HEVC) hybrid architecture was proposed in the standardization process of HEVC.  ...  By using Naïve-Bayes classifiers, the proposed technique exploits the information gathered in the encoding of the H.264/AVC view to make decisions on the splitting of coding units in HEVC side views.  ...  In order to enable a system which offers 3D functionality, a low overall bit rate, and compatibility with currently existing H.264/AVC-based systems, a multiview H.264/AVC and HEVC hybrid architecture  ... 
doi:10.1007/s11265-016-1156-z fatcat:smfnghsqt5gkhebdftv7edja7e

Design and ARM-Based Implementation of Bitstream-Oriented Chaotic Encryption Scheme for H.264/AVC Video

Zirui Zhang, Ping Chen, Weijun Li, Xiaoming Xiong, Qianxue Wang, Heping Wen, Songbin Liu, Shuting Cai
2021 Entropy  
To satisfy these requirements, an improved bitstream-oriented encryption (BOE) method based chaotic encryption for H.264/AVC video is proposed.  ...  Meanwhile, an ARM-embedded remote real-time video confidential communication system is built for experimental verification in this paper.  ...  Acknowledgments: The authors are thankful to the reviewers for their comments and suggestions to improve the quality of the manuscript.  ... 
doi:10.3390/e23111431 pmid:34828129 pmcid:PMC8621351 fatcat:g3frnfdv5jaehp72vjnpceid2m

High throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systems

Tiago Dias, Sebastian Lopez, Nuno Roma, Leonel Sousa
2011 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation  
An innovative high throughput and scalable multitransform architecture for H.264/AVC is presented in this paper.  ...  Furthermore, such results also showed that this architecture can compute, in realtime, all the above mentioned H.264/AVC transforms for video sequences with resolutions up to UHDV.  ...  for H.264/AVC.  ... 
doi:10.1109/samos.2011.6045465 dblp:conf/samos/DiasLRS11 fatcat:kqpxrpfvrjdxrmqozytpusbeya

Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: the H.264/AVC Deblocking Filter

C. Arbelo, A. Kanstein, S. Lopez, J. F. Lopez, M. Berekovic, R. Sarmiento, J.-Y. Mignolet
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
Deblocking filtering represents one of the most compute intensive tasks in an H.264/AVC standard video decoder due to its demanding memory accesses and irregular data flow.  ...  In this sense, the mapping of this decoder's functionality onto a C-programmable coarse-grained reconfigurable architecture named ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is  ...  ACKNOWLEDGMENT The authors wish to thank IMEC for supporting the student internships which made this work possible, and for providing access to the tools.  ... 
doi:10.1109/date.2007.364587 dblp:conf/date/ArbeloKLLBSM07 fatcat:mfapuuuw65gazgr7cjdogcd7gu

Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

Sergio Saponara, Maurizio Martina, Michele Casula, Luca Fanucci, Guido Masera
2010 Microprocessors and microsystems  
H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, highdefinition TV and DVD-based systems, which require  ...  Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding / Saponara S.; Martina M.; Casula M.; Fanucci L.; Masera G.  ...  The implementation of hardware co-processors, able to sustain real-time and high-quality H.264/AVC video coding, is needed to grant high performance.  ... 
doi:10.1016/j.micpro.2010.06.003 fatcat:3htyd4p7rzdnnppfgwgkejlxye
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