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Partially reconfigurable system-on-chips for adaptive fault tolerance

Shaon Yousuf, Adam Jacobs, Ann Gordon-Ross
2011 2011 International Conference on Field-Programmable Technology  
Due to the runtime flexibility of modern dynamically reconfigurable SRAM-based FPGAs, FPGA devices have become an attractive platform for developing system-on-chips (SoCs) for space applications (space  ...  In this paper, we present a flexible, FPGA-based, adaptive SoC for space system development.  ...  In the area of COTS FPGA-based FT systems, the Remote Exploration Experimentation (REE) project by NASA JPL [2] proposed an FT high performance supercomputer for space using FPGA-based processors and  ... 
doi:10.1109/fpt.2011.6132708 dblp:conf/fpt/YousufJG11 fatcat:h4tcrmws4fc3rn2f6m2zcdil7y

A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures

Małgorzata Michalska, Jani Boutellier, Marco Mattavelli
2015 Procedia Computer Science  
Experimental results validate a many-core platform built by an array of Transport Triggered Architecture processors for exploring the partitioning search space based on the execution trace analysis.  ...  Maximizing the data throughput is a very common implementation objective for several streaming applications.  ...  Introduction A natural method to handle applications characterized by high computational complexity is to implement parallel programs on high performance machines.  ... 
doi:10.1016/j.procs.2015.05.498 fatcat:2vu5cofrxndozlhc6vp3y7yfma

System-Level Performance Estimation for Application-Specific MPSoC Interconnect Synthesis

Po-Kuan Huang, Matin Hashemi, Soheil Ghiasi
2008 2008 Symposium on Application Specific Processors  
We present a framework for development of streaming applications as concurrent software modules running on multi-processors system-on-chips (MPSoC).  ...  We propose an iterative design space exploration mechanism to customize MPSoC architecture for given applications.  ...  A number of leading experts believe that thread-based application development in general, is not a productive and reliable method of developing concurrent software [7] , [8] .  ... 
doi:10.1109/sasp.2008.4570792 dblp:conf/sasp/HuangHG08 fatcat:gh2mwdfghjgp7je4n6l42tvgge

Tabu Search for Partitioning Dynamic Dataflow Programs

Małgorzata Michalska, Nicolas Zufferey, Marco Mattavelli
2016 Procedia Computer Science  
This NP-complete problem is very difficult to solve with high quality close-to-optimal solutions for the very large size of the design space and the possibly large variability of input data.  ...  The approach relies on the use of a simulation tool, capable of estimating the performance for any partitioning configuration exploiting a model of the target architecture and the profiling results.  ...  However, from the perspective of dataflow application designer, the quality of a partitioning configuration is of high importance.  ... 
doi:10.1016/j.procs.2016.05.486 fatcat:k2dbqkbfznfghkybdpqdasv7sm

Continuous Dataflow Update Strategies for Mission-Critical Applications

Charith Wickramaarachchi, Yogesh Simmhan
2013 2013 IEEE 9th International Conference on e-Science  
We validate one of these consistent, low-latency update strategies using the F oε dataflow engine for an eEngineering application from the Smart Power Grid domain, and show its relative performance benefits  ...  In this paper, we formalize different types of dataflow update models for continuous dataflow applications, and identify the qualitative and quantitative metrics to be considered when choosing an update  ...  the Processor Update Type and leave an analysis of other update type for future work due to lack of space.  ... 
doi:10.1109/escience.2013.35 dblp:conf/eScience/WickramaarachchiS13 fatcat:q2yzienphjdn7mwc342sntsodu

Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs

Hervé Yviquel, Alexandre Sanchez, Pekka Jääskeläinen, Jarmo Takala, Mickaël Raulet, Emmanuel Casseau
2014 Journal of Signal Processing Systems  
Dynamic dataflow modeling is attractive to describe complex applications, such as video codecs, at a high level of abstraction.  ...  This paper presents a dataflow-based design approach to implement video codecs on embedded multi-core platforms.  ...  Application model Our methodology relies on a programming model based on the dataflow principle [19, 20] .  ... 
doi:10.1007/s11265-014-0953-5 fatcat:idzwskoqefgatloxppsx5vs6q4

Toward Efficient Execution of RVC-CAL Dataflow Programs on Multicore Platforms

Ilkka Hautala, Jani Boutellier, Teemu Nyländen, Olli Silvén
2018 Journal of Signal Processing Systems  
As an answer to this, the dataflow programming model offers a concurrent and reusability promoting approach for describing applications.  ...  In this work, a runtime for executing Dataflow Process Networks (DPN) on multicore platforms is proposed.  ...  The support for NUMA has been available for schedulers for a while and it is providing fair performance in typical applications [15] .  ... 
doi:10.1007/s11265-018-1339-x fatcat:txjhz22e3vgb3cphnql32wki7y

Guest Editorial: Emerging Technologies and Architectures for Manycore Computing Part 1: Hardware Techniques

Sebastien Le Beux, Paul V. Gratz, Ian O'Connor
2018 IEEE Transactions on Multi-Scale Computing Systems  
The next article, "High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs," authored by Ma»gorzata Michalska, Simone Casale-Brunet, Endri Bezati, and Marco  ...  In the article Illikkal present a systematic traffic modeling and generation methodology for efficient evaluation of NoC-based many-core systems.  ...  The next article, "High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs," authored by Ma»gorzata Michalska, Simone Casale-Brunet, Endri Bezati, and Marco  ... 
doi:10.1109/tmscs.2018.2826758 fatcat:3w6uto7qovfaxpfozlvrsq5oxe

Reconfigurable Computing for Space [chapter]

Donohoe, Gregory W., Lyke James
2010 Aerospace Technologies Advancements  
With today's high-performance FPGAs, however, it is difficult to meet power and radiation requirements for space applications.  ...  Field programmable processor array The Field Programmable Processor Array a reconfigurable processor architecture and chip developed for high-throughput, low-power, on-board data processing for space  ...  Reconfigurable Computing for Space, Aerospace Technologies Advancements, Thawar T.  ... 
doi:10.5772/6939 fatcat:qiy3vly24ndm3eikjutrfzwceu

The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices

Marco Solinas, Rosa M. Badia, Francois Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Sylvain Girbal, Daniel Goodman, Behran Khan (+14 others)
2013 2013 Euromicro Conference on Digital System Design  
TERAFLUX is a Future and Emerging Technology (FET) large-scale project funded by the European Union, which addresses such challenges at once by leveraging the dataflow principles.  ...  Three major challenges have been identified: programmability, manageable architecture design, and reliability.  ...  DDM based processors can achieve high performance with simpler designs, as they do not need complex and expensive modules like out-of-order execution.  ... 
doi:10.1109/dsd.2013.39 dblp:conf/dsd/SolinasBBCEFFGGGGKKLLMMNPTUVWWZG13 fatcat:ubsmqg7w3zdi7f3g7i33ng2oce

Modeling and optimization of dynamic signal processing in resource-aware sensor networks

Shuvra S. Bhattacharyya, William Plishker, Nimish Sane, Chung-Ching Shen, Hsiang-Huang Wu
2011 2011 8th IEEE International Conference on Advanced Video and Signal Based Surveillance (AVSS)  
In this paper, we review a variety of complementary models of computation that are being developed as part of the dataflow interchange format (DIF) project to facilitate efficient and reliable implementation  ...  ., signal processing functionality in which computational structure must be dynamically assessed and adapted based on time-varying environmental conditions, operating constraints or application requirements  ...  More precisely, given a dataflow-based application model G and a given target architecture (collection of processors) A, a DSG D(G) for G is another dataflow graph, which represents a schedule for G on  ... 
doi:10.1109/avss.2011.6027374 dblp:conf/avss/BhattacharyyaPSSW11 fatcat:dhkp4lgotrccpjyguqdceqa63m

An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2

Patrick J. Eibl, Albert Meixner, Daniel J. Sorin
2011 Proceedings of the ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems - SIGMETRICS '11  
High-Level Overview of Argus Argus is a framework for detecting errors within a processor core by checking invariants at run-time.  ...  There is a long history of research in low-cost checkers for the functional units that perform the computations in processor cores.  ... 
doi:10.1145/1993744.1993786 dblp:conf/sigmetrics/EiblMS11 fatcat:ugqwlr676jbejlvpvg5mdnkyou

High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms

Christophe Lucarz, Ghislain Roquier, Marco Mattavelli
2010 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)  
Specifications are provided in the form of an actor and dataflow-based language called CAL.  ...  Nowadays, the design flow of complex signal processing embedded systems starts with a specification of the application by means of a large and sequential program (usually in C/C++).  ...  manual rewriting and results should be sufficiently reliable for driving the appropriate dataflow architecture changes.  ... 
doi:10.1109/dasip.2010.5706264 dblp:conf/dasip/LucarzRM10 fatcat:ufblw2ft6rh3flznr3rh2hs4ry

Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs

Małgorzata Michalska, Nicolas Zufferey, Marco Mattavelli
2016 Journal of Electrical and Computer Engineering  
The problem of partitioning a dataflow program onto a target architecture is a difficult challenge for any application design.  ...  The methodology is based on two elements: an execution model of the dynamic dataflow program which is used as estimation of the performance for the exploration of the large design space and several partitioning  ...  This design space exploration framework performs an estimation of a program execution, based on the analysis of the execution trace.  ... 
doi:10.1155/2016/8536432 fatcat:y4uz6jygs5gfhniqneajzafzcy

A Survey of Coarse-Grained Reconfigurable Architecture and Design

Leibo Liu, Jianfeng Zhu, Zhaoshi Li, Yanan Lu, Yangdong Deng, Jie Han, Shouyi Yin, Shaojun Wei
2019 ACM Computing Surveys  
This article reviews the architecture and design of CGRAs thoroughly for the purpose of exploiting their full potential. First, a novel multidimensional taxonomy is proposed.  ...  and industry, because they offer the performance and energy efficiency of hardware with the flexibility of software.  ...  Based on the evaluation results, the design space exploration is iterated with a loop closure to identify the suitable architecture for target applications.  ... 
doi:10.1145/3357375 fatcat:pqi4d33i6bg45a6llswhwd44qi
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