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Scalability of SOI CMOS technology and circuit to millimeter wave performance
2005
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.
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Passives are integrated in the microprocessor back-end, and the 1.8fF/µm² capacitance density of the Vertical Native Capacitor (VNCAP) in a 90nm SOI CMOS improves by 28%, as compared to a 120 nm SOI CMOS ...
This paper presents the high-frequency performance of the 130 and 90-nm SOI technologies as well as its integration capabilities and scalability. ...
LC and Ring VCO Circuits
B. 320GHz GBW Distributed Amplifier As shown in figure 10 a 9-stage distributed amplifier is integrated in a standard microprocessor 130nm SOI CMOS technology [16] . ...
doi:10.1109/csics.2005.1531780
fatcat:pboz2gd5png3xjvhooar5knwue
A dual-gate 60GHz direct up-conversion mixer with active IF balun in 65nm CMOS
2010
2010 IEEE International Conference on Wireless Information Technology and Systems
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Meanwhile, fully integrated transceivers are designed, fostering the research on up-conversion mixers, where noise figure is less and linearity more of an issue. ...
A multitude of up-conversion mixers in CMOS technology have been published recently (e.g. [1] , [2] , [3] , [4] and [5] ). ...
doi:10.1109/icwits.2010.5612259
fatcat:pt6iouqxqzf2xcjjemhla7mdje
A receiver with in-band IIP3>20dBm, exploiting cancelling of OpAmp finite-gain-induced distortion via negative conductance
2013
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
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Highly linear CMOS radio receivers increasingly exploit linear RF V-I conversion and passive down-mixing, followed by an OpAmp based Transimpedance Amplifier at baseband. ...
We propose to apply a negative conductance to cancel this distortion. In an RF receiver, this increases In-Band IIP 3 from 9dBm to >20dBm, at the cost of 1.5dB extra NF and <10% power penalty. ...
ACKNOWLEDGEMENT This research is supported by the Dutch Technology Foundation STW (i.e. the applied science division of the NWO, and the Ministry of Economic Affairs Technology Program). ...
doi:10.1109/rfic.2013.6569529
fatcat:4vos4bv6ijgrjpj3g66x4wor5m
RFIC 2020 Program
2020
2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
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The feasibility of the proposed concept is validated by designing a fully integrated prototype transmitter including signal processing in 65nm CMOS technology. ...
Abstract: This paper reports on the design of a 60 GHz low-noise amplifier (LNA) with a linear and power efficient gain tuning mechanism in a 65 nm CMOS process. ...
Alavi, Leo C.N. de Vreede; Technische Universiteit Delft, The Netherlands Abstract: We present a 1-3 GHz, 2×13-bit I/Q interleaved direct-digital RF modulator (DDRM) realized in 40 nm CMOS technology as ...
doi:10.1109/rfic49505.2020.9218389
fatcat:fqkpw3oau5gzpoi3gscgb7kwhi
CMOS Integrated Switched-Mode Transmitters for Wireless Communication
[chapter]
2010
Advances in Solid State Circuit Technologies
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PA technology aspects It is only fairly recent that CMOS technology has come up as an alternative for integrated circuit power amplifier design, as CMOS previously was not suitable for PA design due to ...
In this section we will first discuss power amplifier technology issues, and then address losses in switched-mode power amplifiers. ...
The output power (x-axis) represented in dBm, (b). The output power in mW.
Table 1. An overview of CMOS integrated switched-mode power amplifiers. ...
doi:10.5772/8626
fatcat:hv6yajrcsretbapmzeibz5ekfa
Analysis of a 5.5-V Class-D Stage Used in $+$30-dBm Outphasing RF PAs in 130- and 65-nm CMOS
2012
IEEE Transactions on Circuits and Systems - II - Express Briefs
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This paper presents the design and analysis of a 5.5 V Class-D stage used in two fully integrated watt-level, +32.0 dBm and +29.7 dBm, outphasing RF Power Amplifiers (PA) in standard 130 nm and 65 nm CMOS ...
To the authors' best knowledge, the Class-D PAs presented are among the first fully integrated CMOS outphasing PAs reaching +30 dBm and demonstrate state-of-the-art output power and bandwidth. ...
CONCLUSIONS This paper presents the design and analysis of a 5.5 V Class-D stage used in two fully integrated watt-level outphasing RF Power Amplifiers (PA) in standard 1.2/2.5 V 130nm and 65nm CMOS technologies ...
doi:10.1109/tcsii.2012.2228391
fatcat:4uoile26kvhzjgivu3hkady2dy
Millimeter-wave power amplifiers in 45nm CMOS SOI technology
2011
IEEE 2011 International SOI Conference
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Chapter 5 presents a fully-integrated wideband power amplifier implemented in 45 nm CMOS SOI technology. ...
Implementing fully-integrated RF to
millimeter-wave (mm-wave) CMOS power amplifiers (PAs), nevertheless, remains
1. ...
doi:10.1109/soi.2011.6081689
fatcat:3vibcr5at5fa7irjzi7ebytm7e
RFIC 2020 Detailed Author Index
2020
2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
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C D-Band Phased-Array TX and RX Front Ends Utilizing Radio-on-Glass Technology (RMo2B-1) 99 C A 79 C A Reconfigurable SOI CMOS Doherty Power Amplifier Module for Broadband LTE High-Power User Equipment ...
RF Modulator as a Driver for a Common-Gate PA in 40nm CMOS (RTu1C-1) Borremans, M. ...
to 43-GHz SPST Switch with Minimum 50-dB Isolation and +19.6-dBm
Large-Signal Power Handling in 45-nm SOI-CMOS (RMo1D-2)
Calascibetta, Pierino (STMicroelectronics, France) A
107
C A Fully Integrated ...
doi:10.1109/rfic49505.2020.9218303
fatcat:qbk5vxrtingl7dx2tzvhkuz2tu
MMIC Vector Topology Enabling multi RF Functionalities for 5G and Beyond
2021
IEEE Access
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only a few active components, e.g., a sinusoidal local oscillator and a low noise or power amplifier [15]-[20]. ...
This paper presents a vector topology of a monolithic microwave integrated circuit (MMIC) capable of performing several radiofrequency (RF) functionalities essential for future wireless communications ...
The authors have contributed to the dissemination of the Six-Port technology for microwave and mm-wave vector network analysis [29] - [33] , telecommunications and localization [34] - [36] , short-range ...
doi:10.1109/access.2021.3098179
fatcat:b55ut5kzn5gjpjqn5l7jtpdepm
A Quadrature Switched Capacitor Power Amplifier
2016
IEEE Journal of Solid-State Circuits
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This paper presents an all-digital class-G quadrature switched-capacitor power amplifier (Q-SCPA) implemented in 65nm CMOS. ...
The Q-SCPA delivers a peak output power of 20.5 dBm with a peak PAE of 20%. It is measured with a 10-MHz, 64-QAM LTE signal and achieves an ACLR of <-30 dBc, with an EVM < 4%-rms. ...
The nominal supply voltage for CMOS devices is VDD = 1.2 V in the chosen 65nm process technology. ...
doi:10.1109/jssc.2015.2496956
fatcat:6rdzfnqkvjh75jrl7cergej62i
Table of contents
2017
2017 IEEE International Symposium on Circuits and Systems (ISCAS)
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Power Amplifiers Sustainable Smart Ring for Long Term Monitoring of Blood Oxygenation 0.4-to-1--Step Hybrid Integrator for IoT Sensor Applications in 65nm LP CMOS Kinetic AC/DC Converter for Electromagnetic ...
in 65-nm CMOS V-102 -A 60-GHz Low-Noise Variable-Gain Amplifier in a 130-nm BiCMOS Technology for Sixport Applications
V-103 --Reuse Capacitively-Coupled Instrumentation Amplifier for EEG Detection ...
doi:10.1109/iscas.2017.8049750
fatcat:csazlovzq5g4bmzlf7uss65sy4
A 0.2~3.8-GHz Full-Duplex Receiver With More Than ⩾ 25 dB Self-interference Cancellation Using a C-DAC Based Vector Canceller
2021
IEEE Access
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As a proof of concept, a prototype FD receiver is fabricated in CMOS 65 nm technology and measured in chip-on-board (COB) package. ...
This paper presents a 0.2∼3.8-GHz in-band (IB) full-duplex (FD) mixer-first receiver based on a vector self-interference (SI) canceller. ...
FIR filters SIC Mixer-first RX + C-DAC based VM Technology 65nm CMOS 130nm CMOS 130nm CMOS 65nm 65nm 65nm 65nm Canceller Differential Input Yes No Yes No Yes No Yes SIC Domain Analog BB Analog BB RF Analog ...
doi:10.1109/access.2021.3124236
fatcat:tyfjat5345conibrxgegq6zlty
RF CMOS Integrated Circuit: History, Current Status and Future Prospects
2011
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
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As great advancements have been made in CMOS process technology over the past 20 years, RF CMOS circuits operating in the microwave band have rapidly developed from component circuit levels to multiband ...
In this paper, the history and the current status of the development of RF CMOS circuits are reviewed, and the future status of RF CMOS circuits is predicted. ...
Acknowledgments We are all thanks for students and researchers who were or are engaged in studding of the future LSI circuit design with us. ...
doi:10.1587/transfun.e94.a.556
fatcat:4fvaacoeqfc6nhmpgmjg5mrdiq
A CMOS-Compatible Spectrum Analyzer for Cognitive Radio Exploiting Crosscorrelation to Improve Linearity and Noise Performance
2012
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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An existing RF frontend in CMOS-technology with IIP3=+11 dBm and NF=5.5 dB is duplicated and attenuators are put in front to increase linearity to IIP3=+24 dBm. ...
In total, this results in a spurious-free dynamic range of 88 dB in 1 MHz resolution bandwidth. ...
The mixer itself is very linear, with an IIP3 of +26 dBm [8] , [26] , but the IF-amplifiers following the mixer limit the linearity to IIP3=+11 dBm. ...
doi:10.1109/tcsi.2011.2167266
fatcat:fiwujnczlrfavhttkz6rhmfvtm
Least-Squares Phase Predistortion of a +30 dBm Class-D Outphasing RF PA in 65 nm CMOS
2013
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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, applied to one of the first fully integrated +30 dBm Class-D outphasing RF PA in 65nm CMOS. ...
This paper presents a model-based phase-only predistortion method suitable for outphasing radio frequency (RF) power amplifiers (PA). ...
RF PA in 65nm CMOS, which is one of the first fully integrated +30 dBm outphasing PAs. ...
doi:10.1109/tcsi.2012.2230507
fatcat:tpjm6iq2hbhnfhiowctta2nxjq
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