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A formal concurrency model based architecture description language for synthesis of software development tools

Wei Qin, Subramanian Rajagopalan, Sharad Malik
2004 Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools - LCTES '04  
The core layer is based on a formal and flexible microprocessor model -the operation state machine (OSM), which enables MADL to express the concurrency at the operation execution level for a wide range  ...  In order to quickly develop these tools for multiple design points under consideration, it is highly desirable to have them synthesized from formal processor descriptions written in Architecture Description  ...  Architecture description languages (ADLs) were created to convey abstract processor model information to the software development tools.  ... 
doi:10.1145/997163.997171 dblp:conf/lctrts/QinRM04 fatcat:m6ii7un4ifexthibil44cqwa7e

Metropolis: an integrated electronic system design environment

F. Balarin, Y. Watanabe, H. Hsieh, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli
2003 Computer  
Because the model has a precise semantics, it can support several synthesis and formal analysis tools in addition to simulation.  ...  Based on a metamodel with formal semantics that developers can use to capture designs, Metropolis provides an environment for complex electronic-system design that supports simulation, formal analysis,  ...  Here we highlight three of them: tools for formal and simulation-based property verification, and schedule synthesis for concurrent computation.  ... 
doi:10.1109/mc.2003.1193228 fatcat:q345jhhcmvbx3nwnqcxys6sm3e

Multilanguage Specification for System Design [chapter]

A. A. Jerraya, M. Romdhani, Ph. Marrec, F. Hessel, P. Coste, C. Valderrama, G. F. Marchioro, J. M. Daveau, N.-E. Zergainoh
1999 System-Level Synthesis  
Additionally, SDL restricts the communication to the asynchronous model. The recent version of SDL introduces a more generic communication model based on RPC.  ...  StateCharts and Esterel are two synchronous languages. Esterel provides powerful concepts for expressing time and has a large analytical power.  ...  For instance, the language Chill [53] is used for the interpretation of SDL. Finally, most existing language have a formal syntax which is the weakest kind of formal description.  ... 
doi:10.1007/978-94-011-4698-2_3 fatcat:xjrihqmg7bczjlwr2eoaezpxsa

Semi-Automatic RTL Methods for System-on-Chip IP Delivery in the Cyber-Physical System Era

Péter Horváth, Gábor Hosszú, Ferenc Kovács
2016 Periodica Polytechnica Electrical Engineering and Computer Science  
The proposed method is based on a novel modeling language (AMDL) offering a reduced design time while making the microarchitectural details fully accessible for the designer to ensure the required level  ...  This article presents a novel method for creating RTL models of SoCs' reusable macrocells.  ...  Acknowledgement The work was supported by the EuroCPS (No. 644090) Horizon 2020 Project of the EU.  ... 
doi:10.3311/ppee.8527 fatcat:qz76z7jbvnb2pbwjekt3sdry4m

Hardware — Software co-design of embedded telecommunication systems [chapter]

N. S. Voros, S. Tsasakou, C. Valderrama, S. Arab, A. Birbas, M. Birbas, V. Mariatos, A. Andritsou
1998 IFIP Advances in Information and Communication Technology  
In this paper a co-design methodology based on multifonnalism modelling is presented.  ...  The proposed co-design development cycle provides a full blown path from system specification to a virtual prototype of the system under construction.  ...  description languages.  ... 
doi:10.1007/978-0-387-35394-4_24 fatcat:hllxpix4y5h73af3qyn5bjduke

Automatic synthesis of SDL from MSC and its applications in forward and reverse engineering

Nikolai Mansurov
2001 Computer languages  
Wider adoption of formal specification languages in industry is impeded by the lack of support for early development phases and for integration with older, legacy software.  ...  standard Specification and Description Language (SDL).  ...  MSC as a "front-end" formal specification language We suggest using MSC [7] as a "front-end" formal specification language of an FDT-based CASE tool.  ... 
doi:10.1016/s0096-0551(01)00018-2 fatcat:l7qpklsk3jfxpjzcwzpwfa4bhm

A system design methodology for software/hardware co-development of telecommunication network applications

Bill Lin
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
In this paper, we describe a system design methodology for the concurrent development of hybrid software/hardware systems for telecom network applications.  ...  This methodology is based on the results of an investigation and evaluation of an actual industrial system design application for ATM-based broadband networks.  ...  This work is part of a joint collaboration between IMEC and Alcatel-Bell. The author would like to thank M. Genoe, G. Van Wauwe, E. Huyskens, and L.  ... 
doi:10.1145/240518.240645 dblp:conf/dac/Lin96 fatcat:w24c7kebvbethlpvtl2mdggega

The Andres Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems

A. Herrholz, F. Oppenheimer, P. A. Hartmann, A. Schallenberg, W. Nebel, C. Grimm, M. Damm, J. Haase, F. Brame, F. Herrera, E. Villar, I. Sander (+3 others)
2007 2007 International Conference on Field Programmable Logic and Applications  
The design flow is completed by a methodology and tools for automatic hardware and software synthesis for adaptive architectures.  ...  The main objective of ANDRES is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES) based on the modelling language SystemC.  ...  models of computation, languages and tools.  ... 
doi:10.1109/fpl.2007.4380679 dblp:conf/fpl/HerrholzOHSNGDHBHVSJFM07 fatcat:uhneslblq5etlkorfljeiefxcu

Overview of the MPEG Reconfigurable Video Coding Framework

Shuvra S. Bhattacharyya, Johan Eker, Jörn W. Janneck, Christophe Lucarz, Marco Mattavelli, Mickaël Raulet
2009 Journal of Signal Processing Systems  
languages.  ...  However, very little attention has been given to provide a specification formalism that explicitly presents common components between standards, and the incremental modifications of such monolithic standards  ...  MPEG RVC decoder are based on the Cal dataflow model of computation and are: -A Decoder Description (DD) written in FNL describing the architecture of the decoder, in terms of FUs and their connections  ... 
doi:10.1007/s11265-009-0399-3 fatcat:5dhub7pkxvapfmepkmdvrem6y4

SOFHIA: A CAD Environment to Design Digital Control Systems [chapter]

Ricardo J. Machado, João M. Fernandes, Alberto J. Proença
1997 Hardware Description Languages and their Applications  
The main advantages lie on the graphical interface and on the availability of a set of techniques for formal analysis, including the validation and the test of the modelled system.  ...  The environment includes the automatic generation of VHDL code to allow simulation and synthesis on existing CAD tools.  ...  In both cases, the remaining VHDL description is a set of concurrent signal assignments and concurrent ASSERT statements.  ... 
doi:10.1007/978-0-387-35064-6_10 fatcat:hrjukzrpx5bgbb64cqywczvv3a

Formal Modeling and Analysis of AADL Threads in Real Time Maude

F. Belala, M. Benammar, K. Barkaoui, A. Hicheur
2012 Journal of Software Engineering and Applications  
This paper presents, without altering the AADL meta-model, a formal description of static and behavioral aspects of the AADL thread component.  ...  This formalization, based on real-time object-oriented theories, allows not only a precise description of the semantics of threads composition with respect to their timing requirements but also makes possible  ...  The architecture description language AADL (Architecture Analysis and Design Language) [2] is a formal notation for describing the architectural plan of real time embedded system at various abstraction  ... 
doi:10.4236/jsea.2012.512b036 fatcat:gaitzcnmkzbwld47nbrcgm67fa

Knowledge-based software architectures: acquisition, specification, and verification

J.J.P. Tsai, A. Liu, E. Juan, A. Sahay
1999 IEEE Transactions on Knowledge and Data Engineering  
We also discuss various software architecture styles, architecture description languages (ADLs), and features of ADLs that help build better software systems.  ...  Based on our survey results, we give a basis for comparing the various knowledge-based systems and list these comparisons in the form of a table.  ...  ACKNOWLEDGMENTS We thank the anonymous reviewer, whose comments have helped us to improve the presentation of the paper. Jeffrey  ... 
doi:10.1109/69.755628 fatcat:yjbrd5vxmrbrhntjpqkd7yghly

The standard SpecC language

Masahiro Fujita, Hiroshi Nakamura
2001 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01  
With these clarifications given by SpecC version 2.0, varieties of supporting tools for SpecC can consistently and easily be developed.  ...  This paper introduces SpecC language, a system level description language based on C, and its consortium, SpecC Technology Open Consortium (STOC).  ...  We plan to formally release SpecC language version 2.0 in the beginning of 2002. Based on the formal semantics, many supporting tools for SpecC are expected to be available soon.  ... 
doi:10.1145/500001.500019 fatcat:iv3dcraobfc7levkrht443amuy

Save-IDE - A tool for design, analysis and implementation of component-based embedded systems

Severine Sentilles, Anders Pettersson, Dag Nystrom, Thomas Nolte, Paul Pettersson, Ivica Crnkovic
2009 2009 IEEE 31st International Conference on Software Engineering  
Save-IDE supports efficient development of dependable embedded systems by providing tools for design of embedded software systems using a dedicated component model, formal specification and analysis of  ...  The paper presents Save-IDE, an Integrated Development Environment for the development of component-based embedded systems.  ...  The TAE provides the developer with a graphical user interface for creating a formal model of the internal behavior of a SaveCCM element.  ... 
doi:10.1109/icse.2009.5070567 dblp:conf/icse/SentillesPNNPC09 fatcat:r4t26oe25fbnfpkn2uvhaw3fou

UML2.0 Profiles for Embedded Systems and Systems On a Chip (SOCs)

Fateh Boutekkouk, Mohammed Benmohammed, Sebastien Bilavarn, Michel Auguin
2009 Journal of Object Technology  
Software parts are compiled for the target processing elements and hardware parts are translated to an HDL (Hardware Description Language) description, then synthesized into ASICs or FPGAs.  ...  Two separate design flows start concurrently for the software and hardware.  ...  However it still lacks a support for NFPs modelling for both software and hardware, formal analysis, requirements capture and hardware/software interface synthesis.  ... 
doi:10.5381/jot.2009.8.1.a1 fatcat:coirvylxd5amzmiwtz6ymxi6l4
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