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Phase Change and Magnetic Memories for Solid-State Drive Applications

Cristian Zambelli, Gabriele Navarro, Veronique Sousa, Ioan Lucian Prejbeanu, Luca Perniola
2017 Proceedings of the IEEE  
However, due to the increased request for storage density coupled with performance that positions the storage tier closer to the latency of the processing elements, NAND Flash are becoming a serious bottleneck  ...  The state-of-the-art Solid State Drives now heterogeneously integrate NAND Flash and DRAM memories to partially hide the limitation of the non-volatile memory technology.  ...  Yes Yes No Read Time ∼ 20-50 ns 10 ns 25-125 µs Write Time ∼ 20-50 ns 10 ns ∼ 1-5 ms Write Energy per bit 2 pJ 0.02 pJ 10 nJ Erase Time N/A N/A ∼ 2-9 ms Memory Endurance 10 15 ∼ 10 1 5 10 3 -10 5 Retention  ... 
doi:10.1109/jproc.2017.2710217 fatcat:fof3pr2ixjfqdd3f226s4qqh7e

MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices

Arash Tavakkol, Juan Gómez-Luna, Mohammad Sadrosadati, Saugata Ghose, Onur Mutlu
2018 USENIX Conference on File and Storage Technologies  
Third, these simulators do not capture the full end-to-end latency of I/O requests, which can incorrectly skew the results reported for SSDs that make use of emerging non-volatile memory technologies.  ...  Solid-state drives (SSDs) are used in a wide array of computer systems today, including in datacenters and enterprise servers.  ...  Acknowledgments We thank our shepherd Haryadi Gunawi and the anonymous referees for their feedback on this work.  ... 
dblp:conf/fast/TavakkolGSGM18 fatcat:zcewyum2uracdgy2pvjbuxtewy

PicoServer: Using 3D Stacking Technology to Build Energy Efficient Servers [chapter]

Taeho Kgil, David Roberts, Trevor Mudge
2009 Integrated Circuits and Systems  
The multiple memory dies are composed of DRAM. This use of 3D stacks readily facilitates wide low-latency buses between processors and memory.  ...  This chapter introduces an architecture called Picoserver that employs 3D technology to bond one die containing several simple slow processing cores with multiple memory dies sufficient for a primary memory  ...  Although the page read latency into the internal buffer for a SLC NAND Flash page is approximately 25 μs, the transfer latency to read several KBs from a NAND Flash chip is substantially higher.  ... 
doi:10.1007/978-1-4419-0784-4_9 fatcat:pvbdyi5umnbfppfetrojqdmm5a

PicoServer

Taeho Kgil, Ali Saidi, Nathan Binkert, Steve Reinhardt, Krisztian Flautner, Trevor Mudge
2008 ACM Journal on Emerging Technologies in Computing Systems  
The multiple memory dies are composed of DRAM. This use of 3D stacks readily facilitates wide low-latency buses between processors and memory.  ...  This chapter introduces an architecture called Picoserver that employs 3D technology to bond one die containing several simple slow processing cores with multiple memory dies sufficient for a primary memory  ...  Although the page read latency into the internal buffer for a SLC NAND Flash page is approximately 25 μs, the transfer latency to read several KBs from a NAND Flash chip is substantially higher.  ... 
doi:10.1145/1412587.1412589 fatcat:fqz7s2pmffghvjn3g22vmrbdua

Advances in Emerging Memory Technologies: From Data Storage to Artificial Intelligence

Gabriel Molas, Etienne Nowak
2021 Applied Sciences  
It begins with the presentation of stand-alone and embedded memory technology evolution, since the appearance of Flash memory in the 1980s.  ...  Then, the progress of emerging memory technologies (based on filamentary, phase change, magnetic, and ferroelectric mechanisms) is presented with a review of the major demonstrations in the literature.  ...  In the meantime, the emerging memory could be used as an intermediate step between flash and the main memory, as for instance an ultra-fast SSD used to store data with frequent access.  ... 
doi:10.3390/app112311254 fatcat:pg4iqzg4yfc2vb2lh2mgkyqafq

Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

Joo Yun Seo, Yoon Kim, Sang-Ho Lee, Daewoong Kwon, Hee-Do Na, Hyun Chul Sohn, JongHo Lee, Byung-Gook Park
2019 2019 Electron Devices Technology and Manufacturing Conference (EDTM)  
To adopt high-κ layer into 3D NAND, its memory characteristics were evaluated with capacitors and gate-all-around flash memory devices.  ...  Threedimensional (3D) NAND flash memory paved a new way of increasing the memory capacity by stacking cells in three-dimension.  ...  With the program pulse of 14 V for 100 μs and the erase pulse of -13 V for 100 ms, about 2.5 V of memory window can be obtained.  ... 
doi:10.1109/edtm.2019.8731328 fatcat:sc4eunm44bccffmfpzjfuplqea

SSDs Striking Back: The Storage Jungle and Its Implications to Persistent Indexes

Kaisong Huang, Darien Imai, Tianzheng Wang, Dong Xie
2022 Conference on Innovative Data Systems Research  
However, next-generation SSDs are quickly catching up with performance that overlaps with PM, effectively turning the storage hierarchy into a storage jungle.  ...  The recent exciting development of persistent memory (PM) has led to many new proposals that directly operate and persist indexes on the memory bus, potentially removing the need for the storage stack.  ...  ACKNOWLEDGMENTS We thank the anonymous reviewers for their constructive comments.  ... 
dblp:conf/cidr/HuangI0X22 fatcat:yvtpdsgmzfg4bf6n7rrszlbjo4

Resistive Random Access Memory (RRAM)

Shimeng Yu
2016 Synthesis Lectures on Emerging Engineering Technologies  
The write/read schemes are presented and the peripheral circuitry design considerations are discussed. Finally, a 3D integration approach is introduced for building ultra-high density RRAM array.  ...  RRAM technology has made significant progress in the past decade as a competitive candidate for the next generation non-volatile memory (NVM).  ...  NAND Cell Area >100F 2 6F 2 10F 2 <4F 2 (3D) 6~20F 2 4~20F 2 <4F 2 if 3D Multi-bit 1 1 2 3 1 2 2 Voltage <1V <1V >10V >10V <2V <3V <3V Read Time~1ns~10ns~50ns~10µs <10ns <10ns  ... 
doi:10.2200/s00681ed1v01y201510eet006 fatcat:4t62v2pnrvg25nbludmnowsvk4

Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers

Davide Bertozzi, Stefano Di Carlo, Salvatore Galfano, Marco Indaco, Piero Olivo, Paolo Prinetto, Cristian Zambelli
2015 ACM Transactions on Embedded Computing Systems  
NAND flash memories are becoming the predominant technology in the implementation of mass storage systems for both embedded and high-performance applications.  ...  This paper performs a comprehensive quantitative analysis of the benefits provided by the run-time reconfigurability of an MLC NAND flash controller through the combined effect of an adaptable memory programming  ...  Fig. 3 . 3 Fitting results of the NAND flash compact model with experimental data during an ISPP-SV operation featuring 7µs pulses, 1V ISPP.  ... 
doi:10.1145/2629562 fatcat:2msykxn35ne4phtmnw7f3mnjma

Key-Value Stores on Flash Storage Devices: A Survey [article]

Krijn Doekemeijer, Animesh Trivedi
2022 arXiv   pre-print
Flash is cheaper than DRAM and yet has a lower latency and higher throughput than HDDs.  ...  With the increasing need for timely data analysis, performance becomes more and more critical. In the past, these stores were frequently optimised to run on HDD and DRAM devices.  ...  To give an example of how low low-latency is: Z-NAND can achieve a memory-read latency of 3µs, which is reported to be 8x times faster than the fastest page access latency of modern multi-level cell flash  ... 
arXiv:2205.07975v1 fatcat:5sv2j2m3l5hrlnpjohlcxsh574

Phase change memory technology

Geoffrey W. Burr, Matthew J. Breitwisch, Michele Franceschini, Davide Garetto, Kailash Gopalakrishnan, Bryan Jackson, Bülent Kurdi, Chung Lam, Luis A. Lastras, Alvaro Padilla, Bipin Rajendran, Simone Raoux (+1 others)
2010 Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics  
), the role of coding, and possible routes to an ultra-high density PCM technology.  ...  We then address challenges for the technology, including the design of PCM cells for low RESET current, the need to control device-to-device variability, and undesirable changes in the phase change material  ...  Rettner, S.  ... 
doi:10.1116/1.3301579 fatcat:axaan4wdbbhf3a6ii4wrppriba

Nonvolatile Memories Based on Graphene and Related 2D Materials

Simone Bertolazzi, Paolo Bondavalli, Stephan Roche, Tamer San, Sung-Yool Choi, Luigi Colombo, Francesco Bonaccorso, Paolo Samorì
2019 Advanced Materials  
Nonvolatile memories (NVMs) are making inroads into high-capacity storage to replace hard disk drives, fuelling the expansion of the global storage memory market.  ...  Although at this stage most of the proof-of-concept devices investigated do not compete with state-of-the-art devices, a number of promising technological advancements have emerged.  ...  ] − that were claimed to have latencies of ~0.1−1 µs, i.e. 1000 times shorter than flash NAND  ... 
doi:10.1002/adma.201806663 pmid:30663121 fatcat:3pok26mmk5aqxpxb3k3hubcnh4

New Diagnostic Forensic Protocol for Damaged Secure Digital Memory Cards

F. Thomas-Brans, Th. Heckmann, K. Markantonakis, D. Sauveron
2022 IEEE Access  
acoustic microscopes, chemical benches, and, for the first time, infrared cameras.  ...  Finally, a concrete case study is presented using the new forensic decision diagram-based protocol and the panel of techniques available to diagnose a card damage.  ...  ACKNOWLEDGEMENTS This work benefited from government support managed by the National Research Agency under the Investments for the Future program, with the reference ANR-10-LABX-0074-01 Sigma-LIM.  ... 
doi:10.1109/access.2022.3158958 fatcat:i7ffjnc3pfbm5dj65s52s6v2aa

Experimental Investigation of Programmed State Stability in OxRAM Resistive Memories [article]

Georgi Gorine
2018 arXiv   pre-print
Secondly, various experiments and tests are performed searching for a key parameter in order to control memory retention.  ...  From previous studies, HfO-based OxRAM memories showed good endurance properties (with more than 10e9 write cycles), low operating current (as low as 10 uA), and very fast switching (programming pulses  ...  As a conclusive remark, it must be noted that the developed model is a provisional model. References  ... 
arXiv:1810.10528v1 fatcat:3hwlewgy7fardkxgesdbdbztui

PRINS: Resistive CAM Processing in Storage [article]

Leonid Yavits, Roman Kaplan, Ran Ginosar
2019 arXiv   pre-print
We show that PRINS may outperform a reference computer architecture with a bandwidth-limited external storage.  ...  We present PRINS, a novel in-data processing-in-storage architecture based on Resistive Content Addressable Memory (RCAM).  ...  [39] introduced and constructed BlueDBM, combining a flash based storage with in-store processing capability and a low latency high-throughput inter-controller network, and explored its performance  ... 
arXiv:1805.09612v3 fatcat:gjgbvqf3ebc6lhn5abuipkhfey
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