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Diagnostic fault simulation for synchronous sequential circuits

Shung-Chih Chen, Jer Min Jou
1997 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented.  ...  for a very large sequential benchmark circuit, s35932.  ...  Venkataraman for his correction on calculating the diagnostic resolution.  ... 
doi:10.1109/43.594835 fatcat:mrmbywtk3jcjjojahlps73evo4

An algorithm for diagnostic fault simulation

Yu Zhang, Vishwani D. Agrawal
2010 2010 11th Latin American Test Workshop  
We present a new diagnostic fault simulation algorithm that determines the DC of given test vectors and produces a fault dictionary.  ...  For each vector, we begin with detected fault list at each primary output obtained from a convetional fault simulator.  ...  In [14] , a diagnostic fault simulator is constructed for sequential circuits.  ... 
doi:10.1109/latw.2010.5550345 fatcat:dmvxmslpkrdkzawf7cggg6p3x4

2019 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 38

2019 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., and Zorian, Y.  ...  Qureshi, A., TCAD Jan. 2019 177-189 Haselmayr, W., see Grimmer, A., 1216-1225 He, H., see Hou, Y., 1820-1830 He, L., see Campbell, K., 1345-1358 Hellebrand, S., see Kampmann, M., 1956-1968 Herdt,  ...  ., +, TCAD May 2019 809-821 Circuit simulation A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Check- ing Method Using SPICE and ESD Behavior Models.  ... 
doi:10.1109/tcad.2020.2964359 fatcat:qjr6i73tkrgnrkkmtjexbxberm

A diagnostic test generation system

Yu Zhang, Vishwani D. Agrawal
2010 2010 IEEE International Test Conference  
We use a fast diagnostic fault simulation algorithm to find undistinguished fault pairs from a fault list for a given test vector set.  ...  Those vectors are then simulated to determine the DC, followed by repeated applications of diagnostic test generation and simulation. We observe impoved DC in all benchmark circuits.  ...  In [27] , a diagnostic fault simulator is constructed for sequential circuits.  ... 
doi:10.1109/test.2010.5699237 dblp:conf/itc/ZhangA10 fatcat:i4xcxfigfzeddklzvq3zqypxs4

International Test Conference

1986 IEEE Design & Test of Computers  
"Efficient Fault Simulation of CMOS 15A.3 2:30 p.m. "Modeling and Simulation of Delay Circuits with Accurate Models" Faults In CMOS Logic Circuits" V. Break: 3:00 p.m. 17.2 2:00 p.m.  ...  Fabish -Teradyne Inc. analysis and the fault dictionary in a closed feedback loop Higher fault detection in high performance in-circuit test is which improves overall diagnostic efficiency. realized in  ...  Multiple stuck faults authors' approach realizes an excellent diagnostic add a new dimension to the problem.  ... 
doi:10.1109/mdt.1986.294973 fatcat:6dlybbnmgjhqll6rte6uaisnyi

A Monte Carlo simulation flow for SEU analysis of sequential circuits

Meng Li, Ye Wang, Michael Orshansky
2016 Proceedings of the 53rd Annual Design Automation Conference on - DAC '16  
An efficient methodology for soft error analysis of sequential circuits based on Monte Carlo sampling is proposed.  ...  The flow combines logic simulation for latch-level error propagation and stationarity diagnostic and an improved combinational error simulator with a new masking model based on signal controllability.  ...  ACKNOWLEDGEMENTS This work was supported by the National Science Foundation under grant CCF-1255757 and by the Semiconductor Research Corporation under grant 2416.001.  ... 
doi:10.1145/2897937.2897967 dblp:conf/dac/LiWO16 fatcat:7zys56mhmnhobkudv2ektr3x2q

Abstracts of Current Computer Literature

1969 IEEE transactions on computers  
The stores can be used as main memories for small computers or as fast transfer stores shuttling information between a slow external bulk memory and a very fast random access memory in large computers.  ...  Sequential Machines (Circuits) Method for Deriving the Maximum Compatibility Sets for Sequential Circuit Flow Tables 6970 Logical Design of Sequential Machines 6972 -see also Automata Sets Method for  ... 
doi:10.1109/t-c.1969.222790 fatcat:6uoe3hk6ffhxvgnifzisoykq4e

Fault Simulation and Response Compaction in Full Scan Circuits Using HOPE

S.R. Das, C.V. Ramamoorthy, M.H. Assaf, E.M. Petriu, W.-B. Jone, M. Sahinoglu
2005 IEEE Transactions on Instrumentation and Measurement  
This paper presents results on fault simulation and response compaction on ISCAS 89 full scan sequential benchmark circuits using HOPE-a fault simulator developed for synchronous sequential circuits that  ...  These concepts are then applied to designing efficient space compression networks in the case of full scan sequential benchmark circuits using the fault simulator HOPE.  ...  The authors are also thankful to the Associate Editor of this TRANSACTIONS for his helpful suggestions and kind encouragement.  ... 
doi:10.1109/tim.2005.858102 fatcat:43xg4gz24vfr3ngakcijiasavq

A deductive technique for diagnosis of bridging faults

Venkataraman, Fuchs
1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97  
A deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational or full-scan sequential  ...  Results are provided for all large ISCAS89 benchmark circuits.  ...  All experiments were performed on a SUN SPARCStation 20 with 64MB of memory for the full-scan versions of the ISCAS89 sequential benchmark circuits [12] .  ... 
doi:10.1109/iccad.1997.643595 dblp:conf/iccad/VenkataramanF97 fatcat:62hvbdwoizg2je2b46mkjk27oq

2009 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 28

2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., and Gielen, G. G. E., Globally Reliable Variation-Aware Sizing Ko, H.  ...  C., +, TCAD July 2009 941-955 Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design.  ...  ., +, TCAD Aug. 2009 1162-1175 SRAM chips Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design.  ... 
doi:10.1109/tcad.2009.2036802 fatcat:hxyu2mmrnzfnbi6qlt6bklkgku

Structural In-Field Diagnosis for Random Logic Circuits

Alejandro Cook, Melanie Elm, Hans-Joachim Wunderlich, Ulrich Abelein
2011 2011 Sixteenth IEEE European Test Symposium  
The paper at hand closes this gap with a new built-in test method for autonomous in-field testing and in-field diagnostic data collection.  ...  The paper at hand closes this gap with a new built-in test method for autonomous in-field testing and in-field diagnostic data collection.  ...  Table V shows the diagnostic resolution for each circuit averaged over all injected faults.  ... 
doi:10.1109/ets.2011.25 dblp:conf/ets/CookEWA11 fatcat:yttx3tylfrctlpferesv2a53hy

Design for Testability of Circuits and Systems; An overview

Emad Khalil, M. El-Mahlawy, Fawzy Ibrahim, M. Abdel-Azeem
2006 The International Conference on Electrical Engineering  
Exploring testing strategies for digital combinational and sequential circuits, and introduces a comparative study between the common fault models.  ...  Even though the computing power and resources have multiplied dramatically over last few decades, an increasing number of memory elements in VLSI circuits require more effective and powerful sequential  ...  First, the expansion of a sequential circuit into a combinational circuit or finding STG may result in increased complexity and memory requirement.  ... 
doi:10.21608/iceeng.2006.33550 fatcat:y366rbqfhvhqzbgwzucl5wswoq

Abstracts of Current Computer Literature

1971 IEEE transactions on computers  
; Memory Storage Required to Simulate a Nondeterministic Tape-Bounded Turing Machine 8373 Applications of Metal-Nitride-Oxide-Silicon Transistors to Logic Circuits and Nonvolatile Memory Arrays 8384 Programmed  ...  Essential resources involved are time and memory. For a simple model an optimal time and memory scheduling is derived.  ... 
doi:10.1109/t-c.1971.223248 fatcat:2h66e665r5gxvg6ikpxgsbnzqe

A Depth-Universal Circuit

Stephen A. Cook, H. James Hoover
1985 SIAM journal on computing (Print)  
The paper at hand closes this gap with a new built-in test method for autonomous in-field testing and in-field diagnostic data collection.  ...  However, functional diagnosis does not yield sufficient coverage to allow for short repair times and fast reaction on systematic failures in the production.  ...  Table V shows the diagnostic resolution for each circuit averaged over all injected faults.  ... 
doi:10.1137/0214058 fatcat:jdikpab66rc3nfvjpfjc75ioee

Signature-Based SER Analysis and Design of Logic Circuits

Smita Krishnaswamy, Stephen M. Plaza, Igor L. Markov, John P. Hayes
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
AnSER can also compute SER efficiently in sequential circuits by approximating steady-state probabilities and sequential signal observabilities.  ...  We first present a signaturebased CAD framework that incorporates tools for the logic-level Analysis of Soft Error Rate (AnSER) and for Signature-based Design for Reliability (SiDeR).  ...  Using our method, simulating a circuit with g gates for n simulation cycles, and K bit signatures takes time O(Kng). Figure 6 summarizes our simulation algorithm for sequential circuits.  ... 
doi:10.1109/tcad.2008.2009139 fatcat:a6g4gyx6drdwheewfp2tjac7zq
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