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The work leading to this thesis has been performed in the framework of WiComm: Microelectronics for the next generation of wireless communication project which is a part of a Dutch national research program ... For instance, the front-end can first be combined with the divide-by-64 block to fref UP Reset delay DN fdiv Vbias CP f ref PFD CP I out To bond-pad V tune f RF-LO f div_out f div 74.2 pF 5.74 pF 2 kΩ ... 60 GHz I-Q VCO 24 mW Dual-mode ILFD 4 mW (0.8 V supply) Divide-by-64 6 mW PFD & CP 1.8 mW Buffers 32 mW Total (excluding buffers) 41.8 mW Total (including buffers) 73.8 mW Table 6 . 6 3: Summary of ...doi:10.6100/ir657030 fatcat:tolw5no2rbavzf3uj6zlw4uh3y
This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. ... A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching ... The thesis then presented a sub-integer clock-frequency synthesizer architecture that can operate at a high speed from an ultra-low supply. ...doi:10.7916/d8h437m5 fatcat:kffvyp3gjbffzkp6acsnaitrza
A wideband synthesizer covering from 125MHz to 32GHz with a constant performance across the entire frequency range will be presented; the scaling [...] ... Then, a 2.5-GHz ultra-compact (150um x 280um) analog PLL implemented in a 45-nm CMOS technology with a fully integrated LC-VCO and an on-chip passive R-C loop filter will further be used to show that area ... Acknowledgments The authors would like to thank Bell Laboratories, Alcatel-Lucent Technologies for funding and equipment support; Thomas Chen, Pei-ju Mo, Yu-che Yang, Frank Zhang, and Tsung-han Hsieh for assisting with ...doi:10.7916/d8pn9cs2 fatcat:k6oez6hdebcojmrmrj7ejdulxu
Hauptmann for providing me the opportunity to carry out my research work on an interesting and diversified topic, and for all guidance and support. ... Design aspects of charge-pump phase locked loops Nowadays, virtually all ICs for high frequency PLL-based frequency synthesizers utilize a PFD/CP structure. ... In addition to the various noise sources, non-idealities in the combined PFD/CP operation cause feedthrough of the phase detector frequency pd f . It appears as modulation on the VCO tuning voltage. ...doi:10.25673/4982 fatcat:tmf4z3yxf5eybonpw4vadfd43i
working at fixed frequency due to their limited tuning range. ... To achieve these targets and circumvent the limited tuning range of the BAW oscillator, an up-conversion transmitter using wide IF is used. ... TEMP SENS COMP ALGO ADPLL ÷ N RTC ÷ Q ÷ P PA PPA ÷ O ÷ P ÷ M ∆Σ MOD PFD CP RCCR SiRes Osc. 2.32GHz 2.4-2.48GHz BAW-Based PA LC Osc. ...doi:10.5075/epfl-thesis-4980 fatcat:v4z527da6jcgbfhbuq367snasa