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A dual-loop delay-locked loop using multiple voltage-controlled delay lines

Yeon-Jae Jung, Seung-Wook Lee, Daeyun Shim, Wonchan Kim, Changhyun Kim, Soo-In Cho
2001 IEEE Journal of Solid-State Circuits  
This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs).  ...  A reference loop generates quadrature clocks, which are then delayed with controllable amounts by four VCDLs and multiplexed to generate the output clock in a main loop.  ...  His research interests are video signal processing and compression, high-speed digital circuit design, and high-speed locking systems. He is currently working on DVD-PRML system design. Seung-Wook  ... 
doi:10.1109/4.918916 fatcat:dhbcnfmttbcxdm56z2u4plhk3i

A low phase noise dual loop optoelectronic oscillator as a voltage controlled oscillator with phase locked loop

Daryl T. Spencer, Sudharsanan Srinivasan, Aaron Bluestone, Danielle Guerra, Luke Theogarajan, John E. Bowers
2014 2014 IEEE Photonics Conference  
We demonstrate phase noise improvement in a high frequency 20 GHz optoelectronic oscillator through dual delay lines and phase locking to a low frequency oven controlled crystal oscillator.  ...  We present a dual loop OEO operating at 20 GHz that has been stabilized with multiple techniques in the optical domain as well as electronically stabilized as a voltage controlled oscillator (VCO) with  ...  Tunable optical delay lines were placed in each arm to precisely tune the oscillating frequency to a multiple of the reference frequency at the PFD.  ... 
doi:10.1109/ipcon.2014.6995423 fatcat:gykfoo6frjdhpk4enn7dkt66jy

An Ultra-Low Phase-Noise 20-GHz PLL Utilizing an Optoelectronic Voltage-Controlled Oscillator

Aaron Bluestone, Daryl T. Spencer, Sudharsanan Srinivasan, Danielle Guerra, John E. Bowers, Luke Theogarajan
2015 IEEE transactions on microwave theory and techniques  
This paper describes a novel phase-locked loop (PLL) architecture utilizing an optoelectronic oscillator (OEO) as a voltage-controlled oscillator (VCO).  ...  Index Terms-Frequency stability, low phase noise, optoelectronic oscillators (OEOs), phase-locked loops (PLLs).  ...  a voltage-controlled oscillator (VCO) within a PLL.  ... 
doi:10.1109/tmtt.2015.2397890 fatcat:felnksdxtzamxpafe2ynea3cke

All-digital delay-locked loop for 3D-IC die-to-die clock synchronization

Ching-Che Chung, Chi-Yu Hou
2014 Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test  
Index Term all-digital delay-locked loop, through silicon via (TSV), 3D-IC, digitally controlled delay line.  ...  Firstly, after system is reset, the proposed ADDLL uses two high resolution delay lines which composed of digital controlled varactors (DCVs) to compensate for the delay variations in TSVs.  ...  A dual-delay-locked loop (D-DLL) [4] is proposed for die-to-die clock deskew circuit applications. Two analog charge-pump-based DLLs are used in this design.  ... 
doi:10.1109/vlsi-dat.2014.6834902 dblp:conf/vlsi-dat/ChungH14 fatcat:6jk66tbsfzbq3jsyndbazmn3fq

A semidigital dual delay-locked loop

S. Sidiropoulos, M.A. Horowitz
1997 IEEE Journal of Solid-State Circuits  
This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2) phase shift, and large operating range.  ...  The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation.  ...  The components are a voltage controlled delay line (VCDL), a phase detector, a charge pump, and a first-order loop filter.  ... 
doi:10.1109/4.641688 fatcat:c3gwohuzo5efdcz6t43lv6qfnm

A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs

R.-J. YANG
2005 IEICE transactions on electronics  
A wide-range multiphase delay-locked loop (DLL) using mixed-mode voltage-controlled delay lines (VCDLs) is presented.  ...  This DLL using an analog 3-states phase-frequency detector (PFD) and the proposed digital PFD can achieve low jitter operation over a wide frequency range without harmonic locking problems.  ...  Conventional DLLs can only operate over a small range because the range of the voltage-controlled delay line (VCDL) is limited [5] .  ... 
doi:10.1093/ietele/e88-c.6.1248 fatcat:q7hmncqsnfcd7lzw6t4qv27v64

Low-jitter process-independent DLL and PLL based on self-biased techniques

J.G. Maneatis
1996 IEEE Journal of Solid-State Circuits  
Delay-locked loop (DLL) and phase-locked loop (PLL) designs based upon self-biased techniques are presented.  ...  Both the damping factor and the bandwidth to operating frequency ratio are determined completely by a ratio of capacitances.  ...  It is composed of a phase comparator, charge pump, loop filter, bias generator, and voltage controlled delay line.  ... 
doi:10.1109/jssc.1996.542317 fatcat:eyjpmh4bqncedle44ul22yxraq

A 2–4 GHz fast-locking frequency multiplying delay-locked loop

Jongsun Kim, B-H Bae
2017 IEICE Electronics Express  
A new phase detecting controller (PDC) and a dual-path charge pump (CP) have been adopted to achieve shorter locking time and eliminate lock-in fail problems.  ...  A fast-locking fractional-ratio multiplying DLL (FMDLL) for de-skewed on-chip clock frequency multiplication is presented.  ...  (PD), a charge pump (CP), a voltage controlled delay line (VCDL), select logic, and a divide by N divider.  ... 
doi:10.1587/elex.13.20161056 fatcat:phi27imtefdrrixg22lkkulyla

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim
2000 IEEE Journal of Solid-State Circuits  
A replica delay line is attached to a conventional DLL to fully utilize the frequency range of the voltage-controlled delay line.  ...  This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance.  ...  The replica delay line generates a control voltage Vcr to pass to the core DLL. Vcr is used as a reference voltage in the core DLL to lock to the input frequency.  ... 
doi:10.1109/4.826820 fatcat:whbod2cvofdznoevbge3nvmzna

Supply Insensitivity Temperature Sensor for Microprocessor Thermal Monitoring Using Adc-Sar

N.Elakkiya N.Elakkiya
2013 IOSR Journal of Electrical and Electronics Engineering  
Second, it uses delay-locked loops (DLLs) to convert inverter delays to digital temperature outputs: the use of DLLs enables low energy (0.24 J/sample) and high bandwidth ( 5 kilo-samples/s), facilitating  ...  After calibration, measurement errors for 15 chips fabricated in digital CMOS 0.13 m fall -4.0 o C to 4.0 o C within C in a temperature range of 0-100 o C, where the temperature chamber used has a control  ...  The R-DLL, shown in the lower portion, consists of a voltage-controlled delay line (VCDL), a phase detector, and a charge-pump in a closed loop.  ... 
doi:10.9790/1676-530107 fatcat:li4ppqym4jgmnb2bq3zem2nora

Optimum stabilization of self-mode-locked quantum dash lasers using dual optical feedback with improved tolerance against phase delay mismatch

Haroon Asghar, Ehsan Sooudi, Pramod Kumar, Wei Wei, John. G. McInerney
2017 Optics Express  
We experimentally investigate the RF linewidth and timing jitter over a wide range of delay tuning in a self-mode-locked two-section quantum dash lasers emitting at ~ 1.55 micron and operating at ~ 21  ...  the widest delay range, unlike single loop feedback.  ...  Each feedback loop contained an optical delay line combined with a variable optical attenuator and polarization controller.  ... 
doi:10.1364/oe.25.015796 pmid:28789092 fatcat:e47rxbwi2bfgzk5kpvxjz6pdkm

Pulse doublets generated by a frequency-shifting loop containing an electro-optic amplitude modulator

Hongzhi Yang, Marc Vallet, Haiyang Zhang, Changming Zhao, Marc Brunel
2019 Optics Express  
Furthermore, the un-seeded loop driven above threshold also generates mode-locked picosecond pulse doublets with a continuously adjustable delay up to the modulation period.  ...  We demonstrate an original double-pulse regime when the loop length is a multiple of the RF modulation wavelength applied to the modulator.  ...  Besides, such a scheme may be considered when designing pump-probe experiments, since the delay can be voltage-controlled without using moving delay lines.  ... 
doi:10.1364/oe.27.018766 fatcat:ukh6edhds5ad3kn4gi2jy2s67u

A 500 MHz-to-1.2 GHz Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector

Han-Kyu Chi, Moon-Sang Hwang, Byoung-Joo Yoo, Won-Jun Choe, Tae-Ho Kim, Yong-Sam Moon, Deog-Kyoon Jeong
2011 JSTS Journal of Semiconductor Technology and Science  
This paper describes a reset-free delaylocked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector.  ...  Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter.  ...  For shifting phase, the reference DLL generates a proper control voltage for one-cycle-delayed clock, and transfers the control voltage to the replica half delay line of each channel.  ... 
doi:10.5573/jsts.2011.11.2.073 fatcat:sdcigkwntrcrfljaqnbtk7mzja

A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution

C.-K. SEONG, S.-W. LEE, W.-Y. CHOI
2007 IEICE transactions on electronics  
CONVENTIONAL DIGITALLY-CONTROLLED DUAL-LooP I.  ...  In the measurement, the CDR has ±400ppm resolution of the digitally-controlled dual-loop CDR.  ...  Block diagram of a conventional digitally-controlled dual-loop and easily controllable.  ... 
doi:10.1093/ietele/e90-c.1.165 fatcat:xkfpkzchyrbcrdhgbgwtb3ipba

A 33 MHz Fast-Locking PLL with Programmable VCO and Automatic Band Selection for Clock Generator Application

Neeraj Agarwal, Neeru Agarwal, Chih-Wen Lu, Masahito Oh-e
2021 Electronics  
A high-performance dual-loop PLL wide tuning range was realized using an ASIC digital control circuit.  ...  This paper presents a prototype of an auto-ranging phase-locked loop (PLL) with low jitter noise over a wide operating frequency range using the multiband programmable voltage-controlled oscillator (VCO  ...  A classical PLL uses a single large frequency band for a large locking range, and it has a large voltage-controlled oscillator (VCO) gain.  ... 
doi:10.3390/electronics10141743 fatcat:ekccz5ch55bj7i62zuawve2bay
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