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A design of hybrid operating system for a parallel computer with multi-core and many-core processors

Mikiko Sato, Go Fukazawa, Kiyohiko Nagamine, Ryuichi Sakamoto, Mitaro Namiki, Kazumi Yoshinaga, Yuichi Tsujita, Atsushi Hori, Yutaka Ishikawa
2012 Proceedings of the 2nd International Workshop on Runtime and Operating Systems for Supercomputers - ROSS '12  
(process, memory, and I/O management) Hybrid computer system overview • Linux on Multi-core CPU works as Host OS  I/O devices and Many-core resources management • Light Weight OS on Many-core  ...  Outline • Background • Motivation • Design of Multi-core & Many-core system  Hardware architecture  Software architecture • Prototype system and evaluation • Conclusion Background of this study • Supercomputers  ...  Conclusion • We have proposed a system in which the functions for managing the resources of many-core processors are delegated to the Host OS running on multi-core processor in a parallel computing system  ... 
doi:10.1145/2318916.2318927 fatcat:febvtiheona3tckckgnegvuqve

A framework to analyze processor architectures for next-generation on-board space computing

Tyler M. Lovelly, Donavon Bryan, Kevin Cheng, Rachel Kreynin, Alan D. George, Ann Gordon-Ross, Gabriel Mounce
2014 2014 IEEE Aerospace Conference  
The framework provides a foundation for the analysis of a broad and diverse set of processor architectures for potential use in next-generation, on-board space computing.  ...  Due to harsh and inaccessible operating environments, space computing presents many unique challenges with respect to stringent power, reliability, and programmability constraints that limit on-board processing  ...  ACKNOWLEDGMENTS This work was supported in part by the I/UCRC Program of the National Science Foundation under Grant Nos. EEC-0642422 and IIP-1161022.  ... 
doi:10.1109/aero.2014.6836387 fatcat:pdehrlytgra6rkdwm4hwdicdwa

Hybrid multi-core architecture for boosting single-threaded performance

Jun Yan, Wei Zhang
2007 SIGARCH Computer Architecture News  
the potential of multi-core processors.  ...  In the proposed multi-core architecture, while the highperformance VLIW core is used to run code segments with high instruction-level parallelism (ILP) extracted by the compiler; the superscalar core can  ...  for multi-core computing.  ... 
doi:10.1145/1241601.1241603 fatcat:vjzotxsbo5dtvc6oe6wcifxcie

Marrying Many-core Accelerators and InfiniBand for a New Commodity Processor [article]

Konstantin S. Solnushkin, Yuichi Tsujita
2013 arXiv   pre-print
We propose a new heterogeneous processor, equipped with a network controller and designed specifically for HPC.  ...  We then show how it can be used for enterprise computing market, guaranteeing its widespread adoption and therefore low production costs.  ...  Thus we propose a hybrid system, with many-core and multi-core processors within the same compute node. However, MPI is still useful for most applications.  ... 
arXiv:1307.0100v1 fatcat:yxvtz66fcvahvb3wtytdm6nlhe

Data processing in the wake of massive multi-core processors

J Kowalkowski
2014 Journal of Physics, Conference Series  
This paper will describe the use of GPU and massive multi-core, and the changes that result from massive parallelization and the impact on data processing.  ...  Developments in concurrency (massive multi-core, GPU, and architectures such as ARM) are changing the physics computing landscape.  ...  The combination of many-core and multi-core will form a powerful hybrid processor platform. One possible view of a hybrid node is shown in the right diagram of Figure 3 .  ... 
doi:10.1088/1742-6596/513/5/052015 fatcat:vykewd7dtbem5bvnismgec7zta

Specialized Hybrid Chinese Microprocessors for Solving Important Problems of Fundamental Medicine and National Defense

Andrey Molyakov
2021 Biomedical Journal of Scientific & Technical Research  
CT-2 and CT-3 (codenamed "Thunderbolt") were developed by the University of Defense Technologies (NUDT) and built on hybrid multi-core massive multi-threaded microprocessors.  ...  Chinese hybrid microprocessors of this type are not only the basic building block of Petaflops supercomputer, but also a microprocessor for strategic tasks: national defense, fundamental medicine, molecular  ...  Initially, the massively multi-threaded CT-2 microprocessor with asynchronous threads for information systems has also become hybrid, it has enhanced the power of numerical processing -SIMD operations  ... 
doi:10.26717/bjstr.2021.34.005573 fatcat:ovf6gg7t6vepzdkabzwhcqxq4m

Software Development for Parallel and Multi-Core Processing [chapter]

Kenn R.
2012 Embedded Systems - High Performance Systems, Applications and Projects  
Third, with so many software developers not trained nor experienced with developing parallel software, the addition of many differentiated multi-core processors increases the learning curve for developers  ...  The Multi-core Association's goal is to support the multi-core ecosystem which includes vendors of development tools, debuggers, processors, operating systems, compilers, and simulators along with application  ...  Software Development for Parallel and Multi-Core Processing, Embedded Systems -High Performance Systems, Applications and Projects, Dr.  ... 
doi:10.5772/38261 fatcat:3zwgizqp3vgqfa2hn6gyxmuw44

The SABER system for window-based hybrid stream processing with GPGPUs

Alexandros Koliousis, Matthias Weidlich, Raul Castro Fernandez, Alexander L. Wolf, Paolo Costa, Peter Pietzuch
2016 Proceedings of the 10th ACM International Conference on Distributed and Event-based Systems - DEBS '16  
Heterogeneous architectures that combine multi-core CPUs with many-core GPGPUs have the potential to improve the performance of data-intensive stream processing applications.  ...  In this paper, we review the design principles of SABER in terms of its hybrid stream processing model and its architecture for query execution.  ...  This demonstration presents SABER [16] , a hybrid relational stream processing engine in Java that executes streaming SQL queries on both a multi-core CPU and a many-core GPGPU.  ... 
doi:10.1145/2933267.2933291 dblp:conf/debs/KoliousisWFWCP16 fatcat:mdxbmdygunay5ihstlm57m2jxm

FPGA on FPGA: Implementation of Fine-grained Parallel Genetic Algorithm on Field Programmable Gate Array

A. AL-Marakeby
2013 International Journal of Computer Applications  
A system with 9 processor cores has consumed 63% of the chip logic elements. Fig.6 shows a randomly initialized, and a final solution for the TSP problem.  ...  The designed processor core for Fine-grained PGA has a high performance in the terms of speed and consumption of FPGA chip resources.  ... 
doi:10.5120/13867-1725 fatcat:57gdqu4cb5gstfmvpzrvso35bm

Sunway supercomputer architecture towards exascale computing: analysis and practice

Jiangang Gao, Fang Zheng, Fengbin Qi, Yajun Ding, Hongliang Li, Hongsheng Lu, Wangquan He, Hongmei Wei, Lifeng Jin, Xin Liu, Daoyong Gong, Fei Wang (+5 others)
2021 Science China Information Sciences  
Moreover, this paper proposes the Sunway computer architecture towards exascale computing in which the many-core processor, network chipset and software system are all domestically-designed.  ...  This paper first analyzes the main requirements of exascale computing on the aspects of the parallel computing application and supercomputing center operation.  ...  Programming Challenges To maximize the computing performance of many-core processors, a reduced design scheme for architecture is adopted, which is different from that of multi-core processors.  ... 
doi:10.1007/s11432-020-3104-7 fatcat:ocmhnpa2dng2lhqhldgbcdfw2a

Designing an Efficient Kernel-Level and User-Level Hybrid Approach for MPI Intra-Node Communication on Multi-Core Systems

Lei Chai, Ping Lai, Hyun-Wook Jin, Dhabaleswar K. Panda
2008 2008 37th International Conference on Parallel Processing  
Architectures of Multi-core Processors• H.  ...  -Being used by more than 750 organizations world wide, including many of the top 500 supercomputers -For example, Ranger system at Texas Advanced Computing Center (TACC) ranked 4 th in June '08 ranking  ... 
doi:10.1109/icpp.2008.16 dblp:conf/icpp/ChaiLJP08 fatcat:hmcamfherffsbd5jmwv7tzi2my

Efficient algorithm design on hybrid CPU-FPGA architecture for high performance computing

Jean Shilpa V, P.K. Jawahar
2021 International Journal of Systems Control and Communications  
Experimental results prove that the efficiency of the designed hybrid processor with efficient task based scheduling algorithm yields a 53% increase in the speed of execution with multi-threading and 52%  ...  It employs cores with varying capabilities to achieve high performance computation. This paper proposes a hybrid structure of CPU and FPGA (HCF) heterogeneous, hard and soft-core custom processor.  ...  Abdur Rahman Crescent Institute of science and technology for giving an opportunity to evaluate the system using Xilinx Vivado simulator and Zedboard.  ... 
doi:10.1504/ijscc.2021.10035685 fatcat:w3eovue6lndqhnrxman4o7az3q

Scaling Algebraic Multigrid Solvers: On the Road to Exascale [chapter]

Allison H. Baker, Robert D. Falgout, Todd Gamblin, Tzanio V. Kolev, Martin Schulz, Ulrike Meier Yang
2011 Competence in High Performance Computing 2010  
Our experiences on modern multi-core machines show that significant challenges must be addressed for AMG to perform well on such machines.  ...  Algebraic Multigrid (AMG) solvers are an essential component of many large-scale scientific simulation codes.  ...  machine with two hex-core AMD Opteron processors, and a BlueGene/P system with a single quad-core PowerPC processor per node.  ... 
doi:10.1007/978-3-642-24025-6_18 dblp:conf/chpc/BakerFGK0Y10 fatcat:q433fc5hzfc4xkhbaqmtwxiu7a

Heterogeneous multi-core platform for consumer multimedia applications

P. Kollig, C. Osborne, T. Henriksson
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
This paper presents a multi-core SoC architecture for consumer multimedia applications.  ...  The successful usage of a heterogeneous multi-core SoC platform is presented and it is shown how specific challenges such as inter-processor communication and real-time performance guarantees in physically  ...  The latter two categories are better suited for multimedia because there is a high level of fine-grained data parallelism in many of the algorithms and a system typically is constructed as a pipeline of  ... 
doi:10.1109/date.2009.5090857 dblp:conf/date/KolligOH09 fatcat:owaqbujdtvh6tlgts563yfe2ru

Special Issue: Exploring Languages for Expressing Medium to Massive On-Chip Parallelism

Gabriele Jost, Alice Koniges
2010 Scientific Programming  
Introduction The many-year trend of increasing processor speed has ended, and high-performance computing (HPC) is looking for a path to Exascale computation (i.e., at a rate exceeding 1018 operations per  ...  While many computational scientists believe that the new models may be "MPI + X", where the X denotes a "to be determined" parallel language designed for within the multi-core nodes, and MPI remains across  ... 
doi:10.1155/2010/435943 fatcat:e3e7wn3vojexdejegezcjtfb6e
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