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A delay model for logic synthesis of continuously-sized networks

J. Grodstein, E. Lehman, H. Harkness, B. Grundmann, Y. Watanabe
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)  
Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as constant and makes the cell's delay a linear function of load.  ...  A companion paper [14] uses the computational simplicity to explore a wide search space of algebraic factorings in a mapped network. Our own application is for continuously-sized, fullcustom designs.  ...  Most technology mapping algorithms for logic synthesis have been targeted at technologies with a limited number of cell sizes.  ... 
doi:10.1109/iccad.1995.480156 dblp:conf/iccad/GrodsteinLHGW95 fatcat:u6fkcpth3rdfneinpyzdjlnqca

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits

Eleonora Testa, Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
2021 Proceedings of the 26th Asia and South Pacific Design Automation Conference  
We describe here a novel majority-based logic synthesis flow addressing AQFP technology.  ...  Further, we show an improvement for both area and delay when the MIGs are mapped into the AQFP technology.  ...  ACKNOWLEDGMENTS This research was supported by the SNF grant "Supercool: Design methods and tools for superconducting electronics" -200021_ 1920981, and by the EPFL Open Science Fund.  ... 
doi:10.1145/3394885.3431606 fatcat:wyshksooznaffmm3a4jutw63ye

BDD decomposition for delay oriented pass transistor logic synthesis

R.S. Shelar, S.S. Sapatnekar
2005 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We address the problem of synthesizing pass transistor logic (PTL), with the specific objective of delay reduction, through binary decision diagram (BDD) decomposition.  ...  The decomposition is performed by mapping the BDD to a network flow graph, and then applying the max-flow min-cut technique to bipartition the BDD optimally under a cost function that measures the delay  ...  Therefore, for comparison purposes at the logic synthesis level, where only a single supply voltage and a single temperature is considered, non-linear delay model of the form of Equation 5 is still valid  ... 
doi:10.1109/tvlsi.2005.853601 fatcat:knhq3hr4anepdfjco2kod7zmou

Algorithms for library-specific sizing of combinational logic

Pak K. Chan
1990 Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90  
We examine the problem of choosing the proper sizes from a cell library for the logic elements of a Boolean network to meet timing constraints on the propagation delay along every path from the primary  ...  A backtracking-based algorithm for finding feasible solutions for networks that are not trees is also suggested and evaluated.  ...  Delay models The type of delay models that our algorithms are capable of handling are: 1. model 1: the delay of a logic element is inversely proportional to its size, and is independent of loading and  ... 
doi:10.1145/123186.123302 dblp:conf/dac/Chan90 fatcat:ulq2xy2kzjfjphg6loycectqv4

DRiLLS: Deep Reinforcement Learning for Logic Synthesis [article]

Abdelrahman Hosny, Soheil Hashemi, Mohamed Shalan, Sherief Reda
2019 arXiv   pre-print
Logic synthesis requires extensive tuning of the synthesis optimization flow where the quality of results (QoR) depends on the sequence of optimizations used.  ...  We demonstrate the training of an Advantage Actor Critic (A2C) agent that seeks to minimize area subject to a timing constraint.  ...  In order to model combinatorial optimization for logic synthesis as a game, we define the state of the logic synthesis environment as a set of metrics retrieved from the synthesis tool on a given circuit  ... 
arXiv:1911.04021v2 fatcat:m5yvlqzkwrfo5przeacvs6taaa

Timing closure

Raul Camposano, Oliver Coudert, Patrick Groeneveld, Leon Stok, Ralph H. J. M. Otten
2000 Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00  
Abstract| In this paper we summerize the derivation of the size equations, the key to timing closure. Next we present a n umber of problems when applying these equations in practice.  ...  The main ones are network generation, discrete libraries, size constraints, and resistive i n terconnect.  ...  This leads to a new paradigm in synthesis 2, 7]: any delay imposed by synthesis can be realized, provided that the sizes of the gates can be continuously adjusted, and the imposed delay exceeds the parasitic  ... 
doi:10.1145/368434.368681 dblp:conf/aspdac/CamposanoCGSO00 fatcat:3dvp7tlj3bcxfgl2xiqjzvvsea

A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic

K.S. Lowe, P.G. Gulak
1998 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper presents the first reported joint gate sizing and buffer insertion method for minimizing the delay of power constrained combinational logic networks that can incorporate a mixture of unbuffered  ...  In the method, buffered gates in a network are decided on by an iterative process that uses a sequence of sizing optimizations where after each sizing optimization an update to the selection of buffered  ...  Malm of IBM as well the anonymous referees for their helpful comments on this work.  ... 
doi:10.1109/43.703932 fatcat:wvs2nmma7zddrpxm2bmvlvvwb4

The role of timing verification in layout synthesis

Jacques Benkoski, Andrzej J. Strojwas
1991 Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91  
This tutorial presents an overview of timing verification techniques which are used in the synthesis of IC layout.  ...  Issues which are covered include: delay estimation, transistor sizing, timing-driven placement and routing, circuit extraction, timing analysis and timing simulation.  ...  Note that a path which can be sensitizable for certain values of delays in the network may become false as a result of a change in the delay values.  ... 
doi:10.1145/127601.122895 dblp:conf/dac/BenkoskiS91 fatcat:vluhk6wrcfbtzeti3gzibkci7q

Library-less synthesis for static CMOS combinational logic circuits

Gavrilov, Glebov, Pullela, Moore, Dharchoudhury, Panda, Vijayan, Blaauw
1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97  
Typically, the structures and the sizes of the gates in the library are chosen to yield a good synthesis results over many blocks or even for an entire chip.  ...  Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase.  ...  Observe that for the same delay, the resynthesized circuit consumes much less power than the original circuit from logic synthesis.  ... 
doi:10.1109/iccad.1997.643608 dblp:conf/iccad/GavrilovGPMDPVB97 fatcat:h45ctkmo7nb77h6admjszrxrsu

Planning for performance

Ralph H. J. M. Otten, Robert K. Brayton
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
A shift is proposed in the design of VLSI circuits. In conventional design, higher levels of synthesis produce a netlist, from which layout synthesis builds a mask specification for manufacturing.  ...  In this paper we attempt to quantify this problem for future technologies and propose some solutions for a "constant delay" methodology. 1 Delay can also be reduced by "tapering" the wire, causing some  ...  Acknowledgment: The vision that synthesis should be conducted with guaranteed performance was developed by Lukas van Ginneken.  ... 
doi:10.1145/277044.277071 dblp:conf/dac/OttenB98 fatcat:boutoxuc2bbabpmgqlkn5mss2i

ABC: An Academic Industrial-Strength Verification Tool [chapter]

Robert Brayton, Alan Mishchenko
2010 Lecture Notes in Computer Science  
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs.  ...  A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains.  ...  Acknowledgement This work has been supported in part by SRC contracts 1361.001 and 1444.001, NSF grant CCF-0702668, and the industrial sponsors: Abound Logic, Actel, Altera, Atrenta, Calypto, IBM, Intel  ... 
doi:10.1007/978-3-642-14295-6_5 fatcat:wobetxmdtbbvrlhvn5ihhmqjzu

Global delay optimization using structural choices

Alan Mishchenko, Robert Brayton, Stephen Jang
2010 Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10  
Experimental results for networks mapped into 6-input look-up tables show that the delay is, on average, improved 14% using a realistic delay library for LUTs with variable-pin delays and wire-delay estimation  ...  This paper presents a fast global method for delay optimization after technology mapping.  ...  Since logic synthesis and mapping are often iterated, a more elaborate logic synthesis of the cofactor logic cones is deferred to after the next round of synthesis.  ... 
doi:10.1145/1723112.1723144 dblp:conf/fpga/MishchenkoBJ10 fatcat:blitbqlikzeezfp2dnkd4ytiae

An industrial view of electronic design automation

D. MacMillen, R. Camposano, D. Hill, T.W. Williams
2000 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The automation of the design of electronic systems and circuits [electronic design automation (EDA)] has a history of strong innovation.  ...  In particular, we will focus on four areas that have been key in defining the design methodologies over time: physical design, simulation/verification, synthesis, and test.  ...  Stuck-at faults are easy to model and grow linearly with design size. Most of the years of testing of logic networks have been centered on testing for stuck-at-faults [49] in sequential networks.  ... 
doi:10.1109/43.898825 fatcat:hhk7zrepyfcyxgizvotqck7cei

Power reduction via near-optimal library-based cell-size selection

M Rahman, H Tennakoon, C Sechen
2011 2011 Design, Automation & Test in Europe  
After using state-of-the-art commercial synthesis, the application of our discrete size selection tool results in a dynamic power reduction of 40% (on average) for large industrial designs.  ...  Assuming continuous cell sizes we have robustly achieved global minimization of the total transistor sizes needed to achieve a delay goal, thus minimizing dynamic power (and reducing leakage power).  ...  We propose a new table-lookup delay model derived from existing .lib files by extending the logical effort model [6] .  ... 
doi:10.1109/date.2011.5763293 dblp:conf/date/RahmanTS11 fatcat:lonwej35fjh55glaf3ezucuofu

Timing Challenges for Very Deep Sub-Micron (VDSM) IC

Ichiang Lin, Chien-In Henry Chen
2002 VLSI design (Print)  
Logic synthesis using the cell library models for interconnect delay estimates may be statistically accurate, but can not predict the delay of individual nets accurately.  ...  Compared to half-micron designs, the amount of time spent on timing verification has greatly increased. Cell delays can be accurately estimated during logic synthesis.  ...  Logic synthesis uses the statistical models to estimate the interconnect delays. These estimates may be statistically accurate, but may not predict the delay of a single net accurately.  ... 
doi:10.1080/1065514021000012183 fatcat:wukbgvs5njcqxcsjyj7fq4tfum
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