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Performance Analysis of 6T and 9T SRAM
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<span title="2019-05-18">2019</span>
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arXiv
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SRAM is widely used for on-chip cache memory in microprocessors, game software, computers, workstations, portable handheld devices due to high data speed, low power consumption, low voltage supply, no-refresh ...
The SRAM cell is made up of latch, which ensures that the cell data is preserved as long as power is turned on and refresh operation is not required for the SRAM cell. ...
, cell ratio, pullup ratio, and voltage supply for both the 6T and 9T Static Random Access Memory cells. ...
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Low Power and High Speed 13T SRAM Cell with Bit-Interleaving Capability
<span title="2016-05-17">2016</span>
<i title="Foundation of Computer Science">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/b637noqf3vhmhjevdfk3h5pdsu" style="color: black;">International Journal of Computer Applications</a>
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In this paper a low power single ended 13T SRAM cell has been proposed for bit inter-leaving application. ...
A column aware scheme is used in the cell to achieve stable SRAM cell with better performance than the existing designs. ...
The authors would thank the reviewers and the editors for their careful review and very helpful comments. The CAD tools of SMDP project in MANIT, Bhopal is gratefully acknowledged. ...
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A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell
<span title="">2016</span>
<i title="Institute of Electrical and Electronics Engineers (IEEE)">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a>
</i>
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A novel 8-transistor (8T) static random access memory cell with improved data stability in subthreshold operation is designed. ...
The proposed single-ended with dynamic feedback control 8T static RAM (SRAM) cell enhances the static noise margin (SNM) for ultralow power supply. ...
Still, none of the cell could fulfill the requirement of improving both read and write stability in subthreshold regime for ultralow power applications. ...
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A 0.33-V, 500-kHz, 3.94-$\mu\hbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
<span title="">2012</span>
<i title="Institute of Electrical and Electronics Engineers (IEEE)">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/c352rf3zizflhbzkvxrawww7mu" style="color: black;">IEEE Transactions on Circuits and Systems - II - Express Briefs</a>
</i>
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This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bitline (RPBL) structure and negative bit-line (NBL) write-assist. ...
Index Terms-Negative bit-line (NBL), ripple bit-line (RPBL), subthreshold static random-access memory (SRAM), ultra-low voltage, 9T SRAM cell. ...
Fig. 1 . 1 (a) Schematic of the disturb-free 9T cell [19] and (b) layout of the 9T cell in UMC 40-nm low-power (40LP) CMOS technology. ...
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A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
<span title="">2012</span>
<i title="Institute of Electrical and Electronics Engineers (IEEE)">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cz5rf4o3ezafnl4kjpq643g32e" style="color: black;">IEEE Journal of Solid-State Circuits</a>
</i>
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This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. ...
The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology ...
His research interests include noise suppression design technologies, embedded measurement circuit design, and ultra-low-power SRAM design.
Jihi-Yu ...
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Leakage Immune 9T-SRAM Cell in Sub-threshold Region
<span title="2016-03-01">2016</span>
<i title="Institute of Advanced Engineering and Science">
Bulletin of Electrical Engineering and Informatics
</i>
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The paper presents a variability-aware modified 9T SRAM cell. ...
Thus, comparative analysis exhibits that the proposed design has a significant improvement, thereby achieving high cell stability at 45nm technology. ...
Introduction SRAM (static random access memory) cell stability with voltage scaling is a primary concern in deep sub-micron technology [1] . ...
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Leakage Immune 9T-SRAM Cell in Sub-threshold Region
<span title="2016-03-01">2016</span>
<i title="Institute of Advanced Engineering and Science">
Bulletin of Electrical Engineering and Informatics
</i>
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The paper presents a variability-aware modified 9T SRAM cell. ...
Thus, comparative analysis exhibits that the proposed design has a significant improvement, thereby achieving high cell stability at 45nm technology. ...
Introduction SRAM (static random access memory) cell stability with voltage scaling is a primary concern in deep sub-micron technology [1] . ...
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Leakage Immune 9T-SRAM Cell in Sub-threshold Region
<span title="2016-03-01">2016</span>
<i title="Institute of Advanced Engineering and Science">
Bulletin of Electrical Engineering and Informatics
</i>
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The paper presents a variability-aware modified 9T SRAM cell. ...
Thus, comparative analysis exhibits that the proposed design has a significant improvement, thereby achieving high cell stability at 45nm technology. ...
Introduction SRAM (static random access memory) cell stability with voltage scaling is a primary concern in deep sub-micron technology [1] . ...
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Development of Emulation Network Analyzer Tool for Computer Network Planning
<span title="2016-06-01">2016</span>
<i title="Institute of Advanced Engineering and Science">
Bulletin of Electrical Engineering and Informatics
</i>
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The paper presents a variability-aware modified 9T SRAM cell. ...
Thus, comparative analysis exhibits that the proposed design has a significant improvement, thereby achieving high cell stability at 45nm technology. ...
Introduction SRAM (static random access memory) cell stability with voltage scaling is a primary concern in deep sub-micron technology [1] . ...
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Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture
[chapter]
<span title="2017-05-31">2017</span>
<i title="InTech">
Field - Programmable Gate Array
</i>
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Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. ...
The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAMbased FPGA at system level, device level, and ...
[105] have designed a data aware dynamic 9T SRAM cell to reduce the bitline power consumption. ...
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A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes
<span title="2018-08-28">2018</span>
<i title="Wiley">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fxzyscw7kbbrnftdz4txqtwl4a" style="color: black;">International journal of circuit theory and applications</a>
</i>
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In this work, a data-dependent feedback-cutting-based bit-interleaved 12T static random access memory (SRAM) cell is proposed, which enhances the write margin in terms of write trip point (WTP) and write ...
static noise margin (WSNM) by 2.14× and 8.99× whereas read stability in terms of dynamic read noise margin (DRNM) and read static noise margin (RSNM) by 1.06× and 2.6 ×, respectively, for 0.4 V when compared ...
ACKNOWLEDGMENTS The authors are thankful to Center for International Mobility (CIMO grant no Intia-1-2016-03) and Aalto University, Finland, for their financial support. ...
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40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
<span title="">2014</span>
<i title="Institute of Electrical and Electronics Engineers (IEEE)">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/l6r6h4xpzvh6jkuzrx565pgwgu" style="color: black;">IEEE Transactions on Circuits and Systems Part 1: Regular Papers</a>
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This paper presents a new bit-interleaving 12T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply ...
Data can be written successfully for down to 300 mV. The measured maximum operation frequency is 11.5 MHz with total power consumption of 22 at 350 mV, 25 . ...
ACKNOWLEDGMENT The authors are grateful to CIC, ITRI, NSC, and MOEA, Taiwan, for project support and Taiwan Semiconductor Manufacturing Company (TSMC) for the University Shuttle Program. ...
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Benefits of decomposing wide CMOS transistors into minimum-size gates
<span title="">2009</span>
<i title="IEEE">
2009 NORCHIP
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Ultra Low Voltage SRAM Static random access memory (SRAM) plays a key role in many digital systems, supporting volatile storage in applications such as instruction memory, data memory, cache, FIFOs, register ...
PDP
Power-Delay Product.
PVT
Process, Voltage and Temperature.
RDF
Random Dopant Fluctuations.
SRAM
Static Random Access Memory.
SCE
Short Channel Effect.
SNM
Static Noise Margin. ...
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An Advanced Embedded SRAM Cell with Expanded Read/Write Stability and Leakage Reduction
<span title="2012-09-30">2012</span>
<i title="Institute of Korean Electrical and Electronics Engineers">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dhfzs7wsv5biddom7iwaocnxze" style="color: black;">Journal of IKEEE</a>
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Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. ...
power consumption compared to the standard 6T cell. ...
A data-aware SRAM cell [8] , which circumvents the column-interleaving issue in the write operation, consumes a substantial dynamic power because all the non-selected wordlines in the memory array should ...
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IMPROVED SPEED LOW POWER AND LOW VOLTAGE SRAM DESIGN FOR LDPC APPLICATION CIRCUITS
<span title="">2018</span>
<i title="Taylor's University">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/3vxazte2xfh4vfhg6itjiodlsq" style="color: black;">Journal of Engineering Science and Technology</a>
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There is significant improvement in power dissipation by 99.64 %, delay by 99.9 %, throughput of 490 Mbps and power delay product of 99.96 %. ...
This paper proposed a SRAM design and an attempt has been made to design circuits using dynamic logic and pass transistor logic to obtain better performance in terms of speed, power dissipation and throughput ...
Random Access Memory
VLSI
Static Random Access Memory
VTC
Table 1 . 1 Simulation results of SRAM cell. ...
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