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A comprehensive approach to DRAM power management

Ibrahim Hur, Calvin Lin
2008 High-Performance Computer Architecture  
This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power.  ...  extended to manage power and energy; and (3) for situations in which additional DRAM power reduction is needed, we present a throttling approach that arbitrarily reduces DRAM activity by delaying the  ...  We thank Alper Buyuktosunoglu for his helpful expertise on power consumption. We thank the entire IBM Power5 team, in particular, Cheryl Chunco, Steve Dodson, Gary Morrison, Stephen J.  ... 
doi:10.1109/hpca.2008.4658648 dblp:conf/hpca/HurL08 fatcat:llxlsmnoqndhnpprsut5dtmuzi

Exploring performance, power, and temperature characteristics of 3D systems with on-chip DRAM

Jie Meng, Daniel Rossell, Ayse K. Coskun
2011 2011 International Green Computing Conference and Workshops  
This paper presents a comprehensive framework for exploring the power, performance, and temperature characteristics of 3D systems with on-chip DRAM.  ...  Experimental results show that while DRAM stacking is a promising technique for high-end systems, efficient thermal management strategies are needed in embedded systems with cost or space restrictions  ...  In this paper, we present a comprehensive approach to evaluate performance, power, and temperature for 3D systems with on-chip DRAM.  ... 
doi:10.1109/igcc.2011.6008579 dblp:conf/green/MengRC11 fatcat:vk5edbdawbbe3gkl5udqkdj4y4

Tiered-Latency DRAM (TL-DRAM) [article]

Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu
2016 arXiv   pre-print
The key goal of TL-DRAM is to provide low DRAM latency at low cost, a critical problem in modern memory systems.  ...  To this end, TL-DRAM introduces heterogeneity into the design of a DRAM subarray by segmenting the bitlines, thereby creating a low-latency, low-energy, low-capacity portion in the subarray (called the  ...  In the first approach, the memory controller uses the near segment as a hardware-managed cache for the far segment.  ... 
arXiv:1601.06903v1 fatcat:jirxfkfcqzhq7ehxtkdmcdpbti

Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost [article]

Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu
2018 arXiv   pre-print
We propose mechanisms that use the low-latency segment as a hardware-managed or software-managed cache.  ...  To mitigate the high area overhead of DRAM sensing structures, commodity DRAMs connect many DRAM cells to each sense amplifier through a wire called a bitline.  ...  Many thanks to Uksong Kang, Haksoo Yu, Churoo Park, Jung-Bae Lee, and Joo Sun Choi from Samsung, and Brian Hirano from Oracle, for their helpful comments. We thank the reviewers for their feedback.  ... 
arXiv:1805.03048v1 fatcat:e6se3wyaunhtng3x47w7qg6fqe

Analysis and runtime management of 3D systems with stacked DRAM for boosting energy efficiency

Jie Meng, A. K. Coskun
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
We also present a memory management policy that targets applications with spatial variations in DRAM accesses and performs temperature-aware mapping of memory accesses to DRAM banks. 978-3-9810801-8-6/  ...  The complex interplay between performance, energy, and temperature on 3D systems with on-chip DRAM can only be addressed using a comprehensive evaluation framework.  ...  This work has been in part funded by the Design Automation Conference A. Richard Newton Scholarship.  ... 
doi:10.1109/date.2012.6176545 dblp:conf/date/MengC12 fatcat:eoram6c63zdgxgwcogvajvp3r4

DRAMsim

David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, Kathleen Baynes, Aamer Jaleel, Bruce Jacob
2005 SIGARCH Computer Architecture News  
It also models the power consumption of SDRAM and its derivatives. It can be used as a standalone simulator or as part of a more comprehensive system-level model.  ...  As memory accesses become slower with respect to the processor and consume more power with increasing memory size, the focus of memory performance and power consumption has become increasingly important  ...  It also models the power consumption of SDRAM and its derivatives. It can be used as a stand-alone simulator or as a part of a more comprehensive system-level model.  ... 
doi:10.1145/1105734.1105748 fatcat:iqbvevvhz5aobpkwrlwagauipe

Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy [chapter]

Philip Machanick
2004 Lecture Notes in Computer Science  
The approach used, dreamy memory, is to put DRAM in a lowpower mode, unless it is referenced.  ...  The lowest-energy dreamy simulation used less than 16% of the DRAM energy of the fastest non-dreamy version, a very useful gain, given that DRAM uses significantly more power than the processor in a low-energy  ...  I would like to thank Gernot Heiser for proposing that I investigate energy management using RAMpage.  ... 
doi:10.1007/978-3-540-30102-8_13 fatcat:33jh4rbzizfslcjon345yvivba

Data Structure Engineering For Byte-Addressable Non-Volatile Memory

Ismail Oukid, Wolfgang Lehner
2017 Proceedings of the 2017 ACM International Conference on Management of Data - SIGMOD '17  
Storage Class Memory (SCM) is emerging as a viable alternative to traditional DRAM, alleviating its scalability limits, both in terms of capacity and energy consumption, while being non-volatile.  ...  Hence, SCM has the potential to become a universal memory, blurring well-known storage hierarchies. However, along with opportunities, SCM brings many challenges.  ...  It employs a suspend-test-resume approach and simulates power failures using data replication, similar to shadow memory testing approaches [27] .  ... 
doi:10.1145/3035918.3054777 dblp:conf/sigmod/OukidL17 fatcat:e7n6ze3fmvbsdljdegjj7fog2a

When physical is not real enough

Frank Bellosa
2004 Proceedings of the 11th workshop on ACM SIGOPS European workshop: beyond the PC - EW11  
This position paper argues that policies for physical memory management and for memory power mode control should be relocated to the system software of a programmable memory management controller (MMC)  ...  Our approach dissociates the aspects of memory protection and sharing from the aspect of energy-aware management of real memory.  ...  time-gap between DRAM accesses, the threshold for a transition to a low power state can be determined.  ... 
doi:10.1145/1133572.1133573 dblp:conf/sigopsE/Bellosa04 fatcat:qxfjhs4rnrcofgdak7m67n57da

Managing Hybrid Main Memories with a Page-Utility Driven Performance Model [article]

Yang Li, Hui Wang Carnegie Mellon University, Tsinghua University)
2015 arXiv   pre-print
In this paper, we devise the first mechanism, called UBM (page Utility Based hybrid Memory management), that systematically estimates the system performance benefit of placing a page in DRAM versus NVM  ...  To do this, UBM comprehensively considers access frequency, row buffer locality, and memory level parallelism (MLP) to estimate the application's stall time reduction.  ...  We conclude that the utility metric and utility based mechanism proposed in this paper enables an effective approach to hybrid memory management.  ... 
arXiv:1507.03303v1 fatcat:wnmck4irqjcgtdsoyjpd52ecva

Rank-Aware Dynamic Migrations and Adaptive Demotions for DRAM Power Management

Yanchao Lu, Donghong Wu, Bingsheng He, Xueyan Tang, Jianliang Xu, Minyi Guo
2016 IEEE transactions on computers  
Modern DRAM architectures allow a number of low-power states on individual memory ranks for advanced power management.  ...  We further develop adaptive state demotions by considering all low-power states for each rank and a prediction model to estimate the power-down timeout among states.  ...  ACKNOWLEDGMENTS The authors would like to thank anonymous reviewers for their insightful comments.  ... 
doi:10.1109/tc.2015.2409847 fatcat:3fgltlgepffefmdaeyrwo54pvu

Scheduler-based DRAM energy management

V. Delaluz, A. Sivasubramaniam, M. Kandemir, N. Vijaykrishnan, M. J. Irwin
2002 Proceedings - Design Automation Conference  
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operating modes.  ...  This global view combined with the flexibility of a software approach brings large energy savings at no extra hardware cost.  ...  Section 2 reviews basic concepts related to DRAM power-mode management and summarizes important characteristics of hardware-based power-mode management strategies.  ... 
doi:10.1145/513918.514095 dblp:conf/dac/DelaluzSKVI02 fatcat:qoeh3gq4yjgfppenx72oltjuly

Scheduler-based DRAM energy management

V. Delaluz, A. Sivasubramaniam, M. Kandemir, N. Vijaykrishnan, M.J. Irwin
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operating modes.  ...  This global view combined with the flexibility of a software approach brings large energy savings at no extra hardware cost.  ...  Section 2 reviews basic concepts related to DRAM power-mode management and summarizes important characteristics of hardware-based power-mode management strategies.  ... 
doi:10.1109/dac.2002.1012714 fatcat:zque7ujqejhqjc56gzpmz3i4ne

Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency [article]

Kevin K. Chang, Abdullah Giray Yaglıkçı, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, Onur Mutlu
2018 arXiv   pre-print
We take a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the DRAM supply voltage is lowered below the nominal voltage level specified  ...  The key idea of Voltron is to use a performance model to determine by how much we can reduce the supply voltage without introducing errors and without exceeding a user-specified threshold for performance  ...  We take a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the supply voltage is lowered below the nominal voltage level speci ed by  ... 
arXiv:1805.03175v1 fatcat:fvkh35yxmjflvaqajtypopo3yi

Scheduler-based DRAM energy management

V. Delaluz, A. Sivasubramaniam, M. Kandemir, N. Vijaykrishnan, M. J. Irwin
2002 Proceedings - Design Automation Conference  
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operating modes.  ...  This global view combined with the flexibility of a software approach brings large energy savings at no extra hardware cost.  ...  Section 2 reviews basic concepts related to DRAM power-mode management and summarizes important characteristics of hardware-based power-mode management strategies.  ... 
doi:10.1145/514093.514095 fatcat:xqjxt3td2nderimu3txbyug7f4
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