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Analytical modeling and characterization of deep-submicrometer interconnect

D. Sylvester, Chenming Wu
2001 Proceedings of the IEEE  
A fast Monte Carlo approach to modeling the circuit impact of back-end process variation is presented, providing a better depiction of real 3-performance spreads compared to the traditional skew-corner  ...  Finally, a comprehensive system-level performance model called Berkeley Advanced Chip Performance Calculator (BACPAC) is developed that accounts for a number of relevant deep-submicrometer system design  ...  Cao, and S. Nakagawa for their significant contributions to this work.  ... 
doi:10.1109/5.929648 fatcat:vwdddm5zu5hgtkgdo3ifozrbeu

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

K. Banerjee, S.J. Souri, P. Kapur, K.C. Saraswat
2001 Proceedings of the IEEE  
A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occupying a separate physical level interconnected  ...  Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size.  ...  Im, A. Joshi, and R. Shenoy, all from Stanford University, for several interesting discussions and for providing feedback.  ... 
doi:10.1109/5.929647 fatcat:ibkenr5mvrcn3cwc4mxsnpnbwy

2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26

2018 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
., see 2723-2736 , VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems; TVLSI Feb. 2018 262-271 Hsieh, Y., see Tsai, Y., TVLSI May 2018 945-957  ...  Hsu, K., Chen, Y., Lee, Y., and Chang, S., Contactless Testing for Prebond Interposers; TVLSI June 2018 1005-1014 Hsu, Y., see Liu, Z., 1565-1574 Hu, J., see Wang, Y., TVLSI May 2018 805-817 Hu, J  ...  ., +, TVLSI Jan. 2018 50-62 Physics-Based Compact TDDB Models for Low-k BEOL Copper Interconnects With Time-Varying Voltage Stressing.  ... 
doi:10.1109/tvlsi.2019.2892312 fatcat:rxiz5duc6jhdzjo4ybcxdajtbq

Monolithic transformers for silicon RF IC design

J.R. Long
2000 IEEE Journal of Solid-State Circuits  
Index Terms-Baluns, monolithic transformers and inductors, radio frequency integrated circuit design, silicon technology, transformer circuit models, wireless circuits.  ...  A procedure for estimating the size of a monolithic transformer to meet a given specification is outlined, and circuit examples are used to illustrate the applications of the monolithic transformer in  ...  Hadaway of Nortel Networks and D. Harame of IBM for fabrication support. Fabrication services were provided by Nortel Semiconductor and IBM Microelectronics.  ... 
doi:10.1109/4.868049 fatcat:aplyjsophzf4xejymedcjwis5i

Logic Synthesis [chapter]

2017 Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology  
ACKNOWLEDGMENT e authors thank Vladimir Yutsis for his helpful feedback on Section 1.5.2.  ...  ., and Hutton, M., Stochastic physical synthesis considering pre-routing interconnect uncertainty and process variation for FPGAs, IEEE Transactions on VLSI Systems, 16(2), 124-133, 2008. 101.  ...  Bautz, B. and Lokanadham, S., A slew/load-dependent approach to single-variable statistical delay modeling, International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems  ... 
doi:10.1201/9781315215112-13 fatcat:me52zpnxyfcczh3choo2p4zulm

EDA in IBM: past, present, and future

J. Darringer, E. Davidson, D.J. Hathaway, B. Koenemann, M. Lavin, J.K. Morrell, K. Rahmat, W. Roesner, E. Schanzenbach, G. Tellez, L. Trevillyan
2000 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and  ...  to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.  ...  Kudva, A. Kuehlmann, B. Lee, D. Kung, H. M. Huang, J. Moreno, D. Nelson, D. Ostapko, S. Ponnapalli, J. Parisi, R. Puri, L. Reddy, V. Rodriguez, A. Ruehli, J. Staten, L. Stok, A. Tayyab, and B. Wile.  ... 
doi:10.1109/43.898827 fatcat:4qb63c3ytzbezkzrumy57wbbv4

Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality

Zhan Gao, Min-Chun Hu, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Erik Jan Marinissen
2021 Journal of electronic testing  
In Stage 2, with the DDMs as inputs, cell-aware ATPG generates chip-level test patterns per circuit design that is build up of interconnected instances of library cells.  ...  With the aim to achieve the best test quality, we first propose an approach to identify a comprehensive set, referred to as full set, of potential open- and short-defect locations based on cell layout.  ...  as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made.  ... 
doi:10.1007/s10836-021-05943-3 fatcat:ksw7d4lvqnfbbeoilpk4rtxbqy

Modeling digital substrate noise injection in mixed-signal IC's

E. Charbon, P. Miliozzi, L.P. Carloni, A. Ferrari, A. Sangiovanni-Vincentelli
1999 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
A study was performed on a number of standard benchmark circuits to verify the validity of the assumptions and to measure the accuracy of the obtained power spectra.  ...  Using device-level simulation, every gate in a given library is modeled by means of the signal waveform it injects into the substrate, depending on its input transition scheme.  ...  Gharpurey and A. Saldanha for their support and useful discussions.  ... 
doi:10.1109/43.748160 fatcat:yczuhi7b2vhtdhihpbkydfbl6i

2018 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 65

2018 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
., and Pandey, N  ...  ., +, TCSI Sept. 2018 2842-2855 Model Reduction Using Parameterized Limited Frequency Interval Gramians for 1-D and 2-D Separable Denominator Discrete-Time Systems.  ...  ., +, TCSI Sept. 2018 2856-2868 Model Reduction Using Parameterized Limited Frequency Interval Gramians for 1-D and 2-D Separable Denominator Discrete-Time Systems.  ... 
doi:10.1109/tcsi.2019.2896877 fatcat:3lzpngw2ofdjhiculf7ehrjeam

2020 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 67

2020 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
., +, TCSI Jan. 2020 259-270 Control system synthesis A Novel Approach to State and Unknown Input Estimation for Takagi- Sugeno Fuzzy Models With Applications to Fault Detection.  ...  ., +, TCSI Jan. 2020 60-73 Rapid Simulation of Photonic Integrated Circuits Using Verilog-A Compact Models.  ...  ., +, TCSI Dec. 2020 4295-4308 Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits -Application to Voltage-Controlled Ring Oscillators and Frequency-Based ΣΔ ADCs.  ... 
doi:10.1109/tcsi.2021.3055003 fatcat:kbmst5td2bbvtl7vpbj3knnkri

Attomolar Sensitivity of FET Biosensor Based on Smooth and Reliable Graphene Nanogrids

J. Basu, C. RoyChaudhuri
2016 IEEE Electron Device Letters  
Roy : A two-warehouse EOQ model for deteriorating items and stock dependent demand under conditionally permissible delay in payment in imprecise environment, Advanced Modeling and Optimization, 5(2), 2013  ...  Development of an artificial neural network model on dust propagation in a surface mine and knowledge extraction from the model Pnternational Journal of Engineering and Scientific Research Vol 2 Issue  ...  School of Mechatronics AEROSPACE ENGINEERING AND APPLIED MECHANICS  ... 
doi:10.1109/led.2016.2526064 fatcat:ynbd5zx3czfwfnxrqfm2dd3yfm

2021 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 68

2021 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name.  ...  The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination.  ...  Wu, D., +, TCSI Aug. 2021 3211-3221 Differential algebraic equations Frequency Design of Lossless Passive Electronic Filters: A State-Space For-mulation of the Direct Synthesis Approach.  ... 
doi:10.1109/tcsi.2021.3134605 fatcat:txqhqj7nvnh6pp5dqloynq5jku

An Introduction to Spin Wave Computing [article]

Abdulqader Mahmoud, Florin Ciubotaru, Frederic Vanderveken, Andrii V. Chumak, Said Hamdioui, Christoph Adelmann, Sorin Cotofana
2020 arXiv   pre-print
Spin-wave computing can be considered as a subfield of spintronics, which uses magnetic excitations for computation and memory applications.  ...  Subsequently, we discuss the current status and the challenges to combine spin-wave gates and obtain circuits and ultimately computing systems, considering essential aspects such as gate interconnection  ...  The availability of compact models for spin-wave devices and for transducers is essential for the accurate behavior and performance evaluation of hybrid spin-wave-CMOS circuits with a SPICE-based simulation  ... 
arXiv:2006.12905v2 fatcat:7pgffgqbrnaendnl5uyti6osyq

2020 Index IEEE Transactions on Components, Packaging and Manufacturing Technology Vol. 10

2020 IEEE Transactions on Components, Packaging, and Manufacturing Technology  
Circuit Models for the Inductance of Eight-Terminal Decoupling Capacitors.  ...  ., +, TCPMT March 2020 378-388 Inductance Circuit Models for the Inductance of Eight-Terminal Decoupling Capacitors.  ...  Random forests A Predictive Abnormality Detection Model Using Ensemble Learning in Stencil Printing Process. Alelaumi, S., +, 1560 -1568  ... 
doi:10.1109/tcpmt.2020.3045544 fatcat:cpw36cbjcvernfgyphvprvtsvy

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)

2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
DAC is the premier conference for the presentation of research and development work on tools for designing chips and systems, and new methodologies for circuit and embedded system designs.  ...  It is the preferred conference for presenting next generation electronic circuits and system design experiences.  ...  synthesis techniques for reconfigurable computing High-level synthesis Interconnect and package modeling and extraction Signal integrity and reliability analysis Analog and mixed-signal design tools and  ... 
doi:10.1109/dac.2002.1012583 fatcat:k7r43x5evvakrgbrwohrlbq5x4
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