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NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?
2008
2008 Asia and South Pacific Design Automation Conference
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This paper evaluates the severity of negative bias temperature instability (NBTI) degradation in two major circuit applications: random logic and memory array. ...
On the other hand, NBTI degradation in memory shows much severe effect especially when combined with the impact of random process variation, NBTI can dramatically reduce the READ stability of memory cells ...
Compact Circuit Simulation Models for NBTI In this section, we review the temporal V t model under NBTI degradation using the Reaction Diffusion (RD) framework [2] [3] [4] [5] [6] . ...
doi:10.1109/aspdac.2008.4484047
dblp:conf/aspdac/KangGPR08
fatcat:c47n3tzf3rfhda2s2lgeqaj2jq
A comparative study of reliability for finfet
2018
Facta universitatis - series Electronics and Energetics
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to fit to a comprehensive aging model. ...
The continuous downscaling of CMOS technologies over the last few decades resulted in higher Integrated Circuit (IC) density and performance. ...
Acknowledgement: Sponsored by US Dept. of Defense (ONR and AFOSR). ...
doi:10.2298/fuee1803343s
fatcat:rjyajmi2dzfc5ciw5mpaqqp4vm
A New SPICE Reliability Simulation Method for Deep Submicrometer CMOS VLSI Circuits
2006
IEEE transactions on device and materials reliability
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The accelerated lifetime models help to identify the most degraded transistors in a circuit in terms of the device's terminal voltage and current stress profiles. ...
These advantages will allow the circuit designers to perform a quick and efficient circuit reliability analysis and to develop practical guidelines for reliable electronic designs. ...
ACKNOWLEDGMENT The authors would like to thank the reviewers and the editors of this paper for their insightful comments and practical suggestions on this work. ...
doi:10.1109/tdmr.2006.876572
fatcat:wadkzglzi5a4rc73wo7cmthsge
Hardware/Software Codesign for Energy Efficiency and Robustness: From Error-Tolerant Computing to Approximate Computing
[chapter]
2020
Embedded Systems
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To address these variations, designers resort to excessive margins. These margins are increasing rapidly and eventually obliterating any gains due to device scaling. ...
As a consequence, reduction of margins in design has become an important research challenge. ...
After sensor readouts, the compiler estimates the degradation of PEs using the NBTI models. ...
doi:10.1007/978-3-030-52017-5_22
fatcat:znejh7lidjfpngv726tngonw6q
Ingress of Threshold Voltage-Triggered Hardware Trojan in the Modern FPGA Fabric – Detection Methodology and Mitigation
2020
IEEE Access
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The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its ...
Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. ...
RELATED WORK Extensive research has been undertaken to present a detailed analysis of ageing and performance degradation in integrated circuits. ...
doi:10.1109/access.2020.2973260
fatcat:n2kjanchovhqhbpxaytynf65jy
Transistor Degradations in Very Large-Scale-Integrated CMOS Technologies
[chapter]
2018
Very-Large-Scale Integration
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degradation of transistors through consistent aging-parameter extractions for circuit simulation. ...
From this analysis, a low-pressure end-of-line (EOL) anneal can reduce the saturation level of NBTI degradation, which is believed to be caused by the outward diffusion of hydrogen from the gate regions ...
Acknowledgements The author would like to express his appreciation for the device modeling and reliability group and the DRAM device group of SK hynix for providing valuable measurement data and discussions ...
doi:10.5772/intechopen.68825
fatcat:k7plbtzeyvamvi3rzof6btr4ne
Thermally Aware Design
2007
Foundations and Trends® in Electronic Design Automation
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With greater integration, ...
Nassif, Vidyasagar Nookala, Haifeng Qian, and Tianpei Zhang. ...
Acknowledgments The authors gratefully acknowledge the role of their past collaborations with (alphabetically) Charlie Chung-Ping Chen, Brent Goplen, David J. Lilja, Sani R. ...
doi:10.1561/1500000007
fatcat:faxvr2rvl5dsbii5afys7vw4fe
Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues
2012
17th Asia and South Pacific Design Automation Conference
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In this paper, we describe an interdisciplinary effort toward robust and resilient designs that mitigate the effects of device and circuit parameter variations in order to enhance system performance, energy ...
The semiconductor industry is facing a critical research challenge: design future high performance and energy efficient systems while satisfying historical standards for reliability and lower costs. ...
For example, in [6] , the compact variational lithography modeling is used to explicitly guide PV-OPC. ...
doi:10.1109/aspdac.2012.6165064
dblp:conf/aspdac/ReddiPNB12
fatcat:khckyzmudvc6xfx2lgclvhioke
Robust System Design
2010
2010 23rd International Conference on VLSI Design
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In contrast, today's mainstream systems typically assume that transistors and interconnects operate correctly over their useful lifetime. ...
For coming generations of silicon technologies, several causes of hardware failures, largely benign in the past, are becoming significant at the system-level. 3. ...
Circuit Failure Prediction for Circuit Aging In this section, we illustrate the application of circuit failure prediction for transistor aging induced by Negative Bias Temperature Instability (NBTI ), ...
doi:10.1109/vlsi.design.2010.77
dblp:conf/vlsid/Mitra10
fatcat:5vkftdsnejg5fbylfuhtf62wzu
Robust System Design
2011
IPSJ Transactions on System LSI Design Methodology
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In contrast, today's mainstream systems typically assume that transistors and interconnects operate correctly over their useful lifetime. ...
For coming generations of silicon technologies, several causes of hardware failures, largely benign in the past, are becoming significant at the system-level. 3. ...
Circuit Failure Prediction for Circuit Aging In this section, we illustrate the application of circuit failure prediction for transistor aging induced by Negative Bias Temperature Instability (NBTI ), ...
doi:10.2197/ipsjtsldm.4.2
fatcat:jwoqglwa4fds7gzyhjnixvs7bq
Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software
2016
Proceedings of the IEEE
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We provide a comparative evaluation of methods for deployment across various layers of the system from circuits, architecture, to application software. ...
This article surveys challenges and opportunities in identifying variations, their effects and methods to combat these variations for improved microelectronic devices. ...
For slower variations, compact in situ aging sensors with digital outputs have been proposed to measure NBTI and gate oxide degradation [57] . 2) Coarse-Grained Observability: Replica circuits or external ...
doi:10.1109/jproc.2016.2518864
fatcat:sxrsu3excbdg5p7sk4iczz262y
Employing circadian rhythms to enhance power and reliability
2013
ACM Transactions on Design Automation of Electronic Systems
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This paper presents a novel scheme for saving architectural power by mitigating delay degradations in digital circuits due to bias temperature instability (BTI), inspired by the notion of human circadian ...
In the second, the idle phase, the circuit is power-gated and "put to sleep," enabling BTI recovery. ...
Acknowledgment This work was supported in part by the NSF under award CCF-1017778 and the SRC under contract 2012-TJ-2234. ...
doi:10.1145/2491477.2491482
fatcat:ifcbm3wvhzhmrjv7rilrji2auq
Silicon Dating
[article]
2020
arXiv
pre-print
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To address the challenge of detecting recycled devices pre-deployment, we develop Silicon Dating: a low-overhead classifier for detecting recycled integrated circuits using Static Random-Access Memory ...
We observe that over time, software running on a device imprints its unique data patterns into SRAM through analog-domain changes; we measure the level and direction of this change through SRAM power-on ...
The content of the information does not necessarily reflect the position or the policy of the Government, and no official endorsement should be inferred. ...
arXiv:2009.04002v1
fatcat:4qluugjktvgy7biwr4ufmy6hv4
2020 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 39
2020
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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., +, TCAD Nov. 2020 4252-4265 CMOS digital integrated circuits A Macromodeling Approach for Analog Behavior of Digital Integrated Circuits. ...
., +, TCAD Aug. 2020 1607-1620 Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits. ...
Entropy-Directed Scheduling for FPGA High-Level Synthesis. Shen, M., +, TCAD Oct. 2020 2588 -2601 FLASH: Fast, Parallel, and Accurate Simulator for HLS. ...
doi:10.1109/tcad.2021.3054536
fatcat:wsw3olpxzbeclenhex3f73qlw4
2020 Subject Index IEEE Transactions on Applied Superconductivity Vol. 30
2020
IEEE transactions on applied superconductivity
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Strong-Coupled Electromagnetic-Thermal Model for HTS Bulk and Its Uses to Study the Dynamic Characteristics of a Linear HTS Maglev Bearing. ...
., +, TASC Oct. 2020 1301505
qSSTA: A Herbst,
H.F., +, TASC Oct. 2020 1100504
Integrated circuit modeling
JOINUS: A User-Friendly Open-Source Software to Simulate Digital Super-
conductor Circuits. ...
Superconducting tapes T-A-Formulation ...
doi:10.1109/tasc.2020.3044716
fatcat:mp6e2vaew5fl7hezsc2pagq7im
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