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A Combinatorial Approach to X-Tolerant Compaction Circuits

Yuichiro Fujiwara, Charles J. Colbourn
<span title="">2010</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/niovmjummbcwdg4qshgzykkpfu" style="color: black;">IEEE Transactions on Information Theory</a> </i> &nbsp;

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Through the formulation of a combinatorial model of X-compact, novel design techniques are developed for X-codes to detect a specified maximum number of errors in the presence of a specified maximum number  ...  The theoretical foundations of X-codes, employed in an X-tolerant compaction technique called X-compact, are examined.  ...  The fundamental problem in X-tolerant response compaction is to design an X-compact matrix with large compaction ratio that detects faulty circuit behavior.  ... 
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Yuichiro Fujiwara, Charles J. Colbourn. "A Combinatorial Approach to X-Tolerant Compaction Circuits." IEEE Transactions on Information Theory 56.7 (2010) 3196-3206

The genotypic complexity of evolved fault-tolerant and noise-robust circuits

Morten Hartmann, Pauline C. Haddow, Per Kristian Lehre
<span title="">2007</span> <i title="Elsevier BV"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dbxvzia7tzcdzoff4xmqtr4qrq" style="color: black;">Biosystems (Amsterdam. Print)</a> </i> &nbsp;

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Circuits investigated herein are designed to be tolerant to faults or robust to noise, using an evolutionary algorithm. A major challenge is to improve the scalability of the approach.  ...  Herein, we measure the genotypic complexity of circuits evolved for tolerance to faults or noise, in order to uncover how that tolerance affects the complexity of the circuits.  ...  This simple scheme assures a pure feed-forward network and thus combinatorial circuits. The last gates in the netlist are connected to the circuit output.  ... 
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Morten Hartmann, Pauline C. Haddow, Per Kristian Lehre. "The genotypic complexity of evolved fault-tolerant and noise-robust circuits." Biosystems (Amsterdam. Print) 87.2-3 (2007) 224-232

Encoding trade-offs and design toolkits in quantum algorithms for discrete optimization: coloring, routing, scheduling, and other problems [article]

Nicolas PD Sawaya, Albert T Schmitz, Stuart Hadfield
<span title="2022-03-28">2022</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>

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, as compared to previous approaches, which we demonstrate with a number of examples.  ...  Third, we design low-depth graph-derived partial mixers (GDPMs) up to 16-level quantum variables, demonstrating that compact (binary) encodings are more amenable to QAOA than previously understood.  ...  Acknowledgements This research used the resources of the National Energy Research Scientific Computing Center (NERSC), a U.S.  ... 
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Nicolas PD Sawaya, Albert T Schmitz, Stuart Hadfield. "Encoding trade-offs and design toolkits in quantum algorithms for discrete optimization: coloring, routing, scheduling, and other problems." arXiv (2022)

Compact Molecular Simulation on Quantum Computers via Combinatorial Mapping and Variational State Preparation [article]

Diana Chamaki, Mekena Metcalf, Wibe A. de Jong
<span title="2022-05-24">2022</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>

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A notable observation regards the number of calls to the optimizer needed for the compact simulation compared to the full simulation.  ...  We provide a bijective mapping using combinatoric ranking to bijectively map fermion basis states to qubit basis states and express operators in the standard spin representation.  ...  There exist novel approaches for fault-tolerant computers using a linear combination of unitaries and oracular Hamiltonian encoding, which our combinatoric approach is amenable to.  ... 
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Diana Chamaki, Mekena Metcalf, Wibe A. de Jong. "Compact Molecular Simulation on Quantum Computers via Combinatorial Mapping and Variational State Preparation." arXiv (2022)

Circuit optimization: the state of the art

J.W. Bandler, S.H. Chen
<span title="">1988</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/erxfd52o45errblyxi5hcekfku" style="color: black;">IEEE transactions on microwave theory and techniques</a> </i> &nbsp;

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A unified hierarchical treatment of circuit models forms the basis of the presentation. It exposes tolerance phenomena at different parameter/ response levels.  ...  The concepts of design centering, tolerance assignment, and postproduction tuning in relation to yield enhancement and cost reduction suitable for integrated circuits are discussed.  ...  ACKNOWLEDGMENT The authors would like to thank Dr. K. C. Gupta, Guest Editor of this Special Issue on Computer-Aided Design, for his invitation to write this review paper.  ... 
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J.W. Bandler, S.H. Chen. "Circuit optimization: the state of the art." IEEE transactions on microwave theory and techniques 36.2 (1988) 424-443

Fast Error Propagation Probability Estimates by Answer Set Programming and Approximate Model Counting

Anselm Breitenreiter, Marko Andjelkovic, Oliver Schrape, Milos Krstic
<span title="">2022</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/q7qi7j4ckfac7ehf3mjbso4hne" style="color: black;">IEEE Access</a> </i> &nbsp;

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By an efficient problem encoding, we achieve an input data format similar to a Verilog netlist so that extensive preprocessing is avoided.  ...  By a tight interconnection of our application with the underlying solver, we avoid iterating over fault sites and reduce calls to the solver.  ...  So called ( , δ) counters return an approximate count x which lies in the interval [x(1 + ) −1 , x(1 + )] with probability 1 − δ. is called tolerance, δ is called confidence.  ... 
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Anselm Breitenreiter, Marko Andjelkovic, Oliver Schrape, Milos Krstic. "Fast Error Propagation Probability Estimates by Answer Set Programming and Approximate Model Counting." IEEE Access (2022) 51814-51825

A Provably Secure True Random Number Generator with Built-In Tolerance to Active Attacks

Berk Sunar, William Martin, Douglas Stinson
<span title="">2007</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5jlmyrayyrdazh5awdlsoec77q" style="color: black;">IEEE transactions on computers</a> </i> &nbsp;

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After discussing several misconceptions and apparently insurmountable obstacles, we propose a general model which, under mild assumptions, will generate provably random bits with some tolerance to adversarial  ...  This paper is a contribution to the theory of true random number generators based on sampling phase jitter in oscillator rings.  ...  The Urn Model -a Combinatorial Approach The combined signal is sampled to provide a random bitstream. The sampling of this combined signal Ψ is modeled as follows.  ... 
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Citation

Berk Sunar, William Martin, Douglas Stinson. "A Provably Secure True Random Number Generator with Built-In Tolerance to Active Attacks." IEEE transactions on computers 56.1 (2007) 109-119

The Cell Matrix: an architecture for nanocomputing

Lisa J K Durbeck, Nicholas J Macias
<span title="2001-08-22">2001</span> <i title="IOP Publishing"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dtyhvneiqnak7lq5kh2hd4cjme" style="color: black;">Nanotechnology</a> </i> &nbsp;

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fully fault tolerant and selfassembling circuit on general purpose cell matrix platform • Want to tolerate anywhere, and more of them • Try using a full system rebuild Approach • Devices require configuration  ...  and its connections, then repeat x times to grow a matrix • Matrix is a functional substrate • Spatial instead of temporal distribution • Programming is similar to standard digital circuit design • Fine-grained  ... 
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Lisa J K Durbeck, Nicholas J Macias. "The Cell Matrix: an architecture for nanocomputing." Nanotechnology (2001) 217-230

Advanced RF and Microwave Design Optimization: A Journey and a Vision of Future Trends

Jose E. Rayas-Sanchez, Slawomir Koziel, John W. Bandler
<span title="">2021</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/7olj765suncftjzx7gz3u4era4" style="color: black;">IEEE Journal of Microwaves</a> </i> &nbsp;

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To address these major challenges, we venture into the development of sophisticated optimization approaches, exploiting confined and dimensionally reduced surrogate vehicles, automated feature-engineering-based  ...  Our journey starts in the 1960s, with the emergence of formal numerical optimization algorithms for circuit design.  ...  The simplest space reduction approach is to consider single-objective optima x k * obtained by considering one design objective at a time, k = 1, …, N obj .  ... 
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Jose E. Rayas-Sanchez, Slawomir Koziel, John W. Bandler. "Advanced RF and Microwave Design Optimization: A Journey and a Vision of Future Trends." IEEE Journal of Microwaves 1.1 (2021) 481-493

Evolution of fault-tolerant and noise-robust digital designs

M. Hartmann, P.C. Haddow
<span title="">2004</span> <i title="Institution of Engineering and Technology (IET)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/i6gaqnnagndt7pf6mxgezspaka" style="color: black;">IEE Proceedings - Computers and digital Techniques</a> </i> &nbsp;

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It is able to automatically generate digital circuit designs and even circuits that are robust to noise and faults.  ...  Also included is a short overview of some recent work illustrating the robustness and tolerance of bio-inspired hardware systems. The authors are with the  ...  That input is connected to the output of a random gate in the circuit prior to the mutated gate in the netlist, thus ensuring that the circuit stays strictly combinatorial.  ... 
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M. Hartmann, P.C. Haddow. "Evolution of fault-tolerant and noise-robust digital designs." IEE Proceedings - Computers and digital Techniques 151.4 (2004) 287

Fault Diagnosis in Analog Circuits via Symbolic Analysis Techniques [chapter]

Fawzi M, Bessam Z
<span title="2013-01-09">2013</span> <i title="InTech"> Analog Circuits </i> &nbsp;

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But to generate this we need to perform a Gaussian elimination step. One obvious way is to have a combinatorial search through all columns in . . .  ...  A major development step to the MNA method is to eliminate all redundant variables to generate a compacted or reduced system matrix.  ...  basis according to the swapping procedure in condition a , and a new matrix C results.  ... 
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Fawzi M, Bessam Z. "Fault Diagnosis in Analog Circuits via Symbolic Analysis Techniques." Analog Circuits (2013)

A combinatorial algorithm for performance and reliability analysis using multistate models

M. Veeraraghavan, K.S. Trivedi
<span title="">1994</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5jlmyrayyrdazh5awdlsoec77q" style="color: black;">IEEE transactions on computers</a> </i> &nbsp;

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To make the component repair assumptions less restrictive in combinatorial modeling, we introduce the following approach of creating a dummy multistate component that is a combination of the binary components  ...  MULTIPLIER AND POWER-SUM CIRCUIT Decoding delay (time units) ( inputloutput delay is also counted) Number of modulo- wlvnomials Circuit complexity per cell Silicon arcapercelltt circuit Number  ...  Microcode compaction is the process of combining microoperations into microinstructions in order to reduce the space or time necessary for the execution of a microprogram.  ... 
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M. Veeraraghavan, K.S. Trivedi. "A combinatorial algorithm for performance and reliability analysis using multistate models." IEEE transactions on computers 43.2 (1994) 229-234

Combinatorial Properties of Root-fault Hypertrees

R. Sundara Rajan, R. Jayagopal, Indra Rajasingh, T.M. Rajalaxmi, N. Parthiban
<span title="">2015</span> <i title="Elsevier BV"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cx3f4s3qmfe6bg4qvuy2cxezyu" style="color: black;">Procedia Computer Science</a> </i> &nbsp;

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Combinatorial properties have become more and more important recently in the study of reliability, fault tolerance, randomized routing, and transmission delay in interconnection networks.  ...  We also discuss certain combinatorial properties of root-fault hypertrees.  ...  The classical approach to study routing in interconnection networks is to find the shortest path between the sending station and the receiving station.  ... 
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R. Sundara Rajan, R. Jayagopal, Indra Rajasingh, T.M. Rajalaxmi, N. Parthiban. "Combinatorial Properties of Root-fault Hypertrees." Procedia Computer Science (2015) 1096-1103

Synthesis of Multiplexed Biofluidic Microchips

A.J. Pfeiffer, T. Mukherjee, S. Hauan
<span title="">2006</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/rl7xk4fwazdrred2difr6v3lii" style="color: black;">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</a> </i> &nbsp;

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The authors believe that this approach provides a foundation for future extension to LoC devices in which many different complex chemical operations are performed entirely on-chip.  ...  An approach for full-custom LoC design, which leverages optimal design techniques and system-on-a-chip (SoC) physical design methods, is being developed.  ...  Our approach combines system-on-a-chip (SoC) circuit floorplanning and routing techniques with rigorous subsystem design optimization to develop methods for full-custom LoC design.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcad.2005.855931">doi:10.1109/tcad.2005.855931</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/koi77gmuwzgofawlvqc32s4n5a">fatcat:koi77gmuwzgofawlvqc32s4n5a</a> </span>
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A.J. Pfeiffer, T. Mukherjee, S. Hauan. "Synthesis of Multiplexed Biofluidic Microchips." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25.2 (2006) 321-333

On the Maximum Number of Codewords of X-Codes of Constant Weight Three [article]

Yu Tsunoda, Yuichiro Fujiwara
<span title="2019-03-23">2019</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>

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In the context of circuit testing, an (m, n, d, x) X-code compresses n-bit output data R from the circuit under test into m bits, while allowing for detecting the existence of an up to d-bit-wise anomaly  ...  This is the first result that shows the existence of an infinite sequence of X-codes whose compaction ratio tends to infinity for any fixed d under severe weight restrictions.  ...  The simplest case is when x = 1, where the compactor is only required to tolerate a single X.  ... 
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Yu Tsunoda, Yuichiro Fujiwara. "On the Maximum Number of Codewords of X-Codes of Constant Weight Three." arXiv (2019)

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