67 Hits in 5.4 sec

A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems

Jianliang Gao, Jianxin Wang, Yinhe Han, Lei Zhang, Xiaowei Li
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
In this paper, we propose a clustering-based scheme which implements concurrent trace for debugging Networkon-Chip (NoC) based multicore systems.  ...  Concurrent trace is an emerging challenge when debugging multicore systems. In concurrent trace, trace buffer becomes a bottleneck since all trace sources try to access it simultaneously.  ...  Conclusions In this paper, we proposed a novel clustering-based scheme for concurrent trace in debugging NoC-based multicore systems.  ... 
doi:10.1109/date.2012.6176427 dblp:conf/date/GaoWHZL12 fatcat:zfzhnathgbbttjcj6sxkbs3bay

Multicore enablement for Cyber Physical Systems

Andreas Herkersdorf
2012 2012 International Conference on Embedded Computer Systems (SAMOS)  
This report documents the program and the outcomes of Dagstuhl Seminar 13052 "Multicore Enablement for Embedded and Cyber Physical Systems".  ...  During the seminar the participants from industry and academia actively discussed chances and problems of multicore processors in embedded in cyber-physical systems.  ...  A major requirements for NoCs in embedded systems in predictability. Techniques for predictability range from static scheduling (e.g., time-triggered) to dynamic scheduling (e.g., priority-based).  ... 
doi:10.1109/samos.2012.6404198 dblp:conf/samos/Herkersdorf12 fatcat:73whij7ozbfgpimxz4md3f4jii

QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs

Jaume Joven, Akash Bagdia, Federico Angiolini, Per Strid, David Castells-Rufas, Eduard Fernandez-Alonso, Jordi Carrabina, Giovanni De Micheli
2013 IEEE Transactions on Industrial Informatics  
which has been tailored for a distributed-shared memory ARM clustered NoC-based MPSoC platform.  ...  In this paper, we present a hardware-software QoS-driven reconfigurable parallel computing framework, i.e., the NoC services, the runtime QoS middleware API and our ocMPI library and its tracing support  ...  In HPC, performance analysis and optimization specially in multicore systems is often based on the analysis of traces.  ... 
doi:10.1109/tii.2012.2222035 fatcat:26afuvlu7je5pdx2kmreq4mgxe

A Framework for Heuristic Scheduling for Parallel Processing on Multicore Architecture: A Case Study With Multiview Video Coding

Yi Pang, Lifeng Sun, Jiangtao Wen, Fengyan Zhang, Weidong Hu, Wei Feng, Shiqiang Yang
2009 IEEE transactions on circuits and systems for video technology (Print)  
The paper attached deals with a multicore solution for multiview video coding.  ...  Students can work in a group, but each group is limited to a maximum of two.  ...  Acknowledgment The authors would like to thank Intel China Research Center for providing an experimental environment.  ... 
doi:10.1109/tcsvt.2009.2031463 fatcat:t4gvddrsjzc5bdd74yx6gm47w4

parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability

T. Ungerer, C. Bradatsch, M. Gerdes, F. Kluge, R. Jahr, J. Mische, J. Fernandes, P.G. Zaykov, Z. Petrov, B. Boddeker, S. Kehr, H. Regler (+16 others)
2013 2013 Euromicro Conference on Digital System Design  
We aim to achieve a breakthrough in techniques for parallelization of industrial hard real-time programs, provide hard real-time support in system software, WCET analysis and verification tools for multi-cores  ...  with timing-predictable execution. parMERASA will provide a timing analyzable system of parallel hard real-time applications running on a scalable multicore processor. parMERASA goes one step beyond mixed  ...  Therefore, the parMERASA architecture relies on a clustered processor architecture, in which cores are organized in clusters connected through a dedicated NoC.  ... 
doi:10.1109/dsd.2013.46 dblp:conf/dsd/UngererBGKJMFZPBKRHROCBSBLGQPACURP13 fatcat:sc4uy2gpavcgtgj4gz3wxe3oym

A Traffic-Aware Medium Access Control Mechanism for Energy-Efficient Wireless Network-on-Chip Architectures [article]

Naseef Mansoor, Abhishek Vashist, M Meraj Ahmed, Md Shahriar Shamim, Syed Ashraf Mamun, Amlan Ganguly
2018 arXiv   pre-print
Such dynamic adjustment in transmission slots will result in improving the utilization of the wireless medium in a Wireless NoC (WiNoC).  ...  Moreover, to adapt to the varying traffic demands from the applications running on a multicore environment, MAC mechanisms should dynamically adjust the transmission slots of the wireless interfaces (WIs  ...  ACKNOWLEDGMENT This work was supported in part by the US National Science Foundation (NSF) CAREER grant CNS-1553264 and grant CCF-1162123.  ... 
arXiv:1809.07862v1 fatcat:7t2e5mr7bjhbzakyaezw3wiafm

GPGPU-Accelerated Parallel and Fast Simulation of Thousand-Core Platforms

Christian Pinto, Shivani Raghav, Andrea Marongiu, Martino Ruggiero, David Atienza, Luca Benini
2011 2011 11th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing  
We demonstrate our GPGPU simulator on a target architecture composed by several cores (i.e. ARM ISA based), with instruction and data caches, connected through a Network-on-Chip (NoC).  ...  The multicore revolution and the ever-increasing complexity of computing systems is dramatically changing system design, analysis and programming of computing platforms.  ...  for single and multicore platforms.  ... 
doi:10.1109/ccgrid.2011.64 dblp:conf/ccgrid/PintoRMRAB11 fatcat:ltmzdsgnjvcr5kfauecgsegnai

Swifi fault injector for heterogeneous many-core processors

Vanessa Vargas, Pablo Ramos, Jean-François Méhaut, Raoul Velazco
2018 Revista de la Pontificia Universidad Católica del Ecuador  
Los principios CEU fueron adaptados a un procesador heterogéneo de muchos núcleos a pesar de la complejidad de su arquitectura, relacionada principalmente con la gestión de memoria y comunicación entre  ...  El dispositivo de prueba seleccionado es el procesador de múltiples núcleos KALRAY MPPA256 fabricado en tecnología CMOS de 28nm y que posee una arquitectura tipo cluster.  ...  Acknowledgments This work was supported in a part by the Universidad de las Fuerzas Armadas ESPE, by the Secretaría de Educación Superior, Ciencia, Tecnología e Innovación del Ecuador (SENESCYT) STIC-AmSud  ... 
doi:10.26807/revpuce.v0i106.145 fatcat:ch2hmwloqfc5zl2jyjlm2lbbj4

Midpoint routing algorithms for Delaunay triangulations

Weisheng Si, Albert Y. Zomaya
2010 2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS)  
In this paper we propose a power allocation scheme for TLS systems, based on Dynamic Voltage and Frequency Scaling (DVFS), that tries to remedy this inefficiency.  ...  In this paper, we propose a task-based dynamic load-balancing solution for single-and multi-GPU systems.  ...  In this paper we discuss two algorithms based on CAQR and CALU that are adapted to multicore architectures.  ... 
doi:10.1109/ipdps.2010.5470471 dblp:conf/ipps/SiZ10 fatcat:yuchdc4zp5borm5vs7j4rqgmzy

Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor

Hamza Rihani, Matthieu Moy, Claire Maiza, Robert I. Davis, Sebastian Altmeyer
2016 Proceedings of the 24th International Conference on Real-Time Networks and Systems - RTNS '16  
In this paper we introduce a response time analysis technique for Synchronous Data Flow programs mapped to multiple parallel dependent tasks running on a compute cluster of the Kalray MPPA-256 many-core  ...  We extend the Multicore Response Time Analysis (MRTA) framework by deriving a mathematical model of the multilevel bus arbitration policy used by the MPPA.  ...  Acknowledgments This work was funded in part by the grant CAPACITES (PIA-FSN2 n • P3425-146798) from the French Ministère de l'économie, des finances et de l'industrie, the EPSRC project MCC (EP/K011626  ... 
doi:10.1145/2997465.2997472 dblp:conf/rtns/RihaniMMDA16 fatcat:s2wvwbsn5rgtrozcichaew6iqi

NoC2: An Efficient Interfacing Approach for Heavily-communicating NoC-based Systems

Ahmed A. Morgan, Ahmed S. Hassan, M. Watheq El-Kharashi, Ayman Tawfik
2020 IEEE Access  
Current research in interfacing clusters within Hierarchical Networks-on-Chip (HNoC) as well as interfacing NoC-based systems adopts a centralized approach.  ...  Routing inter-NoC traffic through a system to its gateway PE deteriorates the network performance.  ...  Authors also reused trace buffers, which are intended for debugging, to further enhance the performance [28] .  ... 
doi:10.1109/access.2020.3030606 fatcat:3quk2oisyjcuxbl4eqnzbdidi4

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Javad Zarrin, Rui L. Aguiar, João Paulo Barraca
2017 Simulation modelling practice and theory  
Furthermore, the design of architecture simulators for manycore systems involve methods and techniques from various interdisciplinary research areas, which in turn brings more challenges in different aspects  ...  In this paper, we present the challenges for simulating future large scale manycore environments, and we investigate the adequacy of current modeling and simulation tools, methodologies and techniques.  ...  across any MPI-enabled cluster of multiprocessor and multicore machines.  ... 
doi:10.1016/j.simpat.2016.12.014 fatcat:j2acoyv235awfjkz6w7krvzh44

Compiling Scilab to high performance embedded multicore systems

Timo Stripf, Oliver Oey, Thomas Bruckschloegl, Juergen Becker, Gerard Rauwerda, Kim Sunesen, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Olivier Sentieys, Nikolaos Kavvadias (+5 others)
2013 Microprocessors and microsystems  
The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of  ...  a Scilab-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from a high level of abstraction.  ...  for parallel and concurrent computer systems.  ... 
doi:10.1016/j.micpro.2013.07.004 fatcat:pdh6kpwp25galdrdtvpv45l2cy

Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters [article]

Florian Glaser, Giuseppe Tagliavini, Davide Rossi, Germain Haugou, Qiuting Huang, Luca Benini
2020 arXiv   pre-print
In this work, we describe a light-weight hardware-accelerated synchronization and communication unit (SCU) for tightly-coupled clusters of processors.  ...  Shared-L1-memory multiprocessor clusters are a promising architecture, delivering performance in the order of GOPS and over 100 GOPS/W of energy-efficiency.  ...  In order to retain a global address space (for, e.g., debugging purposes), all base units are as well accessible from every core and from outside the cluster through the peripheral LINT.  ... 
arXiv:2004.06662v1 fatcat:d2ydh3olenhgljvwxpqavak54y

An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration

F. Angiolini, J. Ceng, R. Leupers, F. Ferrari, C. Ferri, L. Benini
2006 Proceedings of the Design Automation & Test in Europe Conference  
In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs).  ...  openness and flexibility in terms of design space exploration. 1  ...  ASIPs alone cannot unfortunately be a full answer to the SoC design woes. In fact, understanding the performance issues in a multicore system brings the challenge to a new level.  ... 
doi:10.1109/date.2006.244000 dblp:conf/date/AngioliniCLFFB06 fatcat:kjfkgmhbyfcgrpvfxfvwvbh3qq
« Previous Showing results 1 — 15 out of 67 results