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A case for random shortcut topologies for HPC interconnects

Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova
2012 2012 39th Annual International Symposium on Computer Architecture (ISCA)  
The best results are obtained when adding random links to a ring topology, meaning that good random shortcut topologies can easily be generated for arbitrary numbers of switches.  ...  Finally, we discuss and quantify practical challenges for random shortcut topologies, including routing scalability and larger physical cable lengths.  ...  Our goal in this work is to make a case for using random shortcuts when designing network topologies for HPC systems, which we term "Random Shortcut Topologies."  ... 
doi:10.1109/isca.2012.6237016 dblp:conf/isca/KoibuchiMAHC12 fatcat:gn5k7edymbehde2abrlnwmxcqa

A case for random shortcut topologies for HPC interconnects

Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova
2012 SIGARCH Computer Architecture News  
The best results are obtained when adding random links to a ring topology, meaning that good random shortcut topologies can easily be generated for arbitrary numbers of switches.  ...  Finally, we discuss and quantify practical challenges for random shortcut topologies, including routing scalability and larger physical cable lengths.  ...  Our goal in this work is to make a case for using random shortcuts when designing network topologies for HPC systems, which we term "Random Shortcut Topologies."  ... 
doi:10.1145/2366231.2337179 fatcat:rzl4nazetzad5hlpju7wbovyqm

Layout-conscious random topologies for HPC off-chip interconnects

M. Koibuchi, I. Fujiwara, H. Matsutani, H. Casanova
2013 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)  
The first method randomly swaps link endpoints for a given non-random topology for which a good physical layout is known.  ...  In this work we propose two new methods for generating random topologies and their physical layout on a floorplan: randomize links after optimizing the physical layout, or optimize the layout after randomizing  ...  Topologies of HPC Systems A few topologies are traditionally used to interconnect compute nodes in most HPC systems, and these topologies can be used to interconnect high-radix switches [13] .  ... 
doi:10.1109/hpca.2013.6522343 dblp:conf/hpca/KoibuchiFMC13 fatcat:lkozfi554fffrfvxfgomoj2pc4

Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects

Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova
2015 IEEE Transactions on Parallel and Distributed Systems  
In this work we propose a new method for creating random topologies without increasing cable length: randomly swap link endpoints in a non-random topology that is already deployed across several cabinets  ...  Random network topologies have been proposed to create low-diameter, low-latency interconnection networks in large-scale computing systems.  ...  This is no longer the case for high-degree topologies, and especially topologies that use random shortcuts.  ... 
doi:10.1109/tpds.2014.2340863 fatcat:fs475xu4wjgbjhtwasrry3yapu

Application Mapping and Scheduling of Uncertain Communication Patterns onto Non-Random and Random Network Topologies

Yao HU, Michihiro KOIBUCHI
2020 IEICE transactions on information and systems  
On the other hand, random network topologies have drawn increasing attention for the use of HPC interconnects.  ...  In this context, we recommend using random network topologies as the communication infrastructures, which have drawn increasing attention for the use of HPC interconnects due to their small diameter and  ...  In this study, besides the above traditional non-random topologies, random topologies are also assumed to be our interconnection networks for application allocation.  ... 
doi:10.1587/transinf.2020pap0006 fatcat:t5ept75md5d3vibfktghqrtybe

Layout-Conscious Expandable Topology for Low-Degree Interconnection Networks

Thao-Nguyen TRUONG, Khanh-Van NGUYEN, Ikki FUJIWARA, Michihiro KOIBUCHI
2016 IEICE transactions on information and systems  
Our discrete-event simulation results show that the proposed topology provides a comparable performance to 2-D Torus for some parallel applications.  ...  The network cost and power consumption of DSN-F modestly increase when compared to the counterpart non-random topologies.  ...  Fabien Chaix, Institute of Computer Science, Foundation for Research and Technology -Hellas, Greece, for his assistance to use the parallel-computer simulator SimGrid.  ... 
doi:10.1587/transinf.2015edp7214 fatcat:ldxadvko5rdyjknrdy5x4ehdiy

Augmenting low-latency HPC network with free-space optical links

Ikki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova
2015 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)  
Various network topologies can be used for deploying High Performance Computing (HPC) clusters.  ...  For a diverse application workload, there are downsides to having a single wired topology.  ...  ACKNOWLEDGMENTS We give a special thanks to Shinichi Ishida, Cyber-Koubou LLC, Japan, for making the FSO terminal prototype; and to Yoshinori Arimoto, National Institute of Information and Communications  ... 
doi:10.1109/hpca.2015.7056049 dblp:conf/hpca/FujiwaraKOMC15 fatcat:cyjmby6wg5frbdlgcinueu5doi

Skywalk: A Topology for HPC Networks with Low-Delay Switches

Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova
2014 2014 IEEE 28th International Parallel and Distributed Processing Symposium  
In this context we define a new network topology, Skywalk, for deploying lowlatency interconnects in upcoming HPC systems.  ...  Skywalk uses randomness to achieve low latency, but does so in a way that accounts for the physical layout of the topology so as to lead to further cable length and thus latency reductions.  ...  In [5] , [14] random topologies have been proposed as a way to reduce latency in HPC interconnects.  ... 
doi:10.1109/ipdps.2014.37 dblp:conf/ipps/FujiwaraKMC14 fatcat:whx3ke6fybh5naq4vstejxj5ba

Wormhole optical network: a new architecture to solve long diameter problem in exascale computer

En Shao, Zhan Wang, Guojun Yuan, Guangming Tan, Ninghui Sun
2019 CCF Transactions on High Performance Computing  
We evaluated WON using both a prototype system and a simulator for the exascale computer.  ...  Therefore, building an interconnection network with high cost performance plays a critical role in building such a large scale system.  ...  The hybrid interconnection infrastructure enables a decompositional interconnection, adjustable topology, and optical resource pool. • We implement a multi-dimension optical shortcut controller that cooperates  ... 
doi:10.1007/s42514-019-00006-8 fatcat:vcavmmjebvdfbgyp35spuqgzjy

A Layout-Oriented Routing Method for Low-Latency HPC Networks

Ryuta KAWANO, Hiroshi NAKAHARA, Ikki FUJIWARA, Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO
2017 IEICE transactions on information and systems  
End-to-end network latency has become an important issue for parallel application on large-scale high performance computing (HPC) systems.  ...  The routing tables contain both physically and topologically nearby neighbor nodes to ensure livelock-freedom and a small number of hops between nodes.  ...  Acknowledgments A part of this work was supported by JSPS KAKENHI Grant Number 15J03374.  ... 
doi:10.1587/transinf.2017pap0019 fatcat:grjv55m3unbwln2hucp2ay3zby

Cabinet Layout Optimization of Supercomputer Topologies for Shorter Cable Length

Ikki Fujiwara, Michihiro Koibuchi, Henri Casanova
2012 2012 13th International Conference on Parallel and Distributed Computing, Applications and Technologies  
For a given topology, using graph clustering algorithms, we group switches logically into cabinets so that the number of inter-cabinet cables is small.  ...  In this study, we study the optimization of the physical layout of topologies of switches on a machine room floor with the goal of reducing cable length.  ...  High-radix Topologies A few topologies are traditionally used to interconnect compute nodes in most HPC systems, and these topologies can be used to interconnect high-radix switches.  ... 
doi:10.1109/pdcat.2012.86 dblp:conf/pdcat/FujiwaraKC12 fatcat:juozrk7mwrfiflrxzg67yjejae

High-throughput, energy-efficient network-on-chip-based hardware accelerators

Turbo Majumder, Partha Pratim Pande, Ananth Kalyanaraman
2013 Sustainable Computing: Informatics and Systems  
By inserting long-range links that act as shortcuts in a regular network-on-chip (NoC) architecture, both the achievable bandwidth and energy efficiency of a multicore platform can be significantly enhanced  ...  Dedicated centers hosting scientific computing tools on a few high-end servers could rely on hardware accelerator co-processors that contain multiple lightweight custom cores interconnected through an  ...  However, the best performance in PSA is reported by a NoC-based implementation [16] owing to its custom core architecture and interconnection topology.  ... 
doi:10.1016/j.suscom.2013.01.001 fatcat:3lilgssw75apbbyda7j7iqd72e

Slim Fly: A Cost Effective Low-Diameter Network Topology [article]

Maciej Besta, Torsten Hoefler
2020 arXiv   pre-print
Finally, we propose deadlock-free routing schemes and physical layouts for large computing centers as well as a detailed cost and power model.  ...  We introduce a high-performance cost-effective network topology called Slim Fly that approaches the theoretically optimal network diameter.  ...  As discussed in Section VII-A, the ideas of random shortcut topologies can be combined with Slim Flies. Jiang et al.  ... 
arXiv:1912.08968v2 fatcat:oyq3jtrdrvbslonkskfa6y243m

A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing

Ryuta KAWANO, Hiroshi NAKAHARA, Seiichi TADE, Ikki FUJIWARA, Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO
2017 IEICE transactions on information and systems  
Inter-switch networks for HPC systems and data-centers can be improved by applying random shortcut topologies with a reduced number of hops.  ...  A heuristic approach to reduce VCs is achieved with a hash table, which improves the scalability of the algorithm compared with our previous work.  ...  Acknowledgments A part of this work was supported by JSPS KAKENHI Grant Number JP 15J03374.  ... 
doi:10.1587/transinf.2016edp7477 fatcat:45r5pdnp7zc5rhlimeycw7f3ei

Slim Fly: A Cost Effective Low-Diameter Network Topology

Maciej Besta, Torsten Hoefler
2014 SC14: International Conference for High Performance Computing, Networking, Storage and Analysis  
towards link failures than comparable Dragonflies. • We show a physical layout for a datacenter or an HPC center network and a detailed cost and energy model. • We provide a library of practical topologies  ...  Finally, we propose deadlock-free routing schemes and physical layouts for large computing centers as well as a detailed cost and power model.  ...  As discussed in Section VII-A, the ideas of random shortcut topologies can be combined with Slim Flies. Jiang et al.  ... 
doi:10.1109/sc.2014.34 dblp:conf/sc/BestaH14 fatcat:7cesqjz2ajbzfcqxu2g5ndopie
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