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A case for dynamic frequency tuning in on-chip networks
2009
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture - Micro-42
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Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for multicores/CMPs. ...
Towards this end, this paper proposes a novel router architecture, where we tune the frequency of a router in response to network load to manage both performance and power. ...
ACKNOWLEDGEMENTS We would like to thank the anonymous reviewers for their reviews and comments in improving this paper. ...
doi:10.1145/1669112.1669151
dblp:conf/micro/MishraIDVED09
fatcat:dpjku5um6fc3tbcpkque473qgy
RAFT: A router architecture with frequency tuning for on-chip networks
2011
Journal of Parallel and Distributed Computing
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With increasing number of cores being integrated on a single die, Network-on-Chips (NoCs) have become the de-facto standard in providing scalable communication backbones for these multi-core chips. ...
We also propose and evaluate a novel fine-grained frequency tuning scheme where we vary the number of virtual-channels in a router dynamically. ...
Acknowledgments We would like to thank the anonymous reviewers for their reviews and comments in improving this paper. ...
doi:10.1016/j.jpdc.2010.09.005
fatcat:dvhpez5scfguxdqjkm6m7eqosq
Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System
2012
Frontiers in Neuroscience
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In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. ...
The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. ...
These measurements were used to plot a tuning curve for the network. Figure 9 shows two tuning curves after learning a linear and forked frequency sweeps at 1.0 ms −1 . ...
doi:10.3389/fnins.2012.00017
pmid:22347163
pmcid:PMC3272652
fatcat:ct6ezvt3ojdxhkjnqo7b2fz7je
Tunable neuromimetic integrated system for emulating cortical neuron models
2011
Frontiers in Neuroscience
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Due to process variation and device mismatch in analog chips, we use a full-custom fitting method in voltage-clamp mode to tune our neuromimetic integrated circuits. ...
In previous work, we designed several neuromimetic chips, including the Galway chip that we used for this paper. ...
Philippe Pouliquen for proofreading the material. ...
doi:10.3389/fnins.2011.00134
pmid:22163213
pmcid:PMC3233664
fatcat:pfqfbkerovfvlce2dy3p27atea
Green DataPath for TCAM-Based Software-Defined Networks
2016
IEEE Communications Magazine
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To this end, aiming to find energy-efficient routing paths for traffic sessions in SDN networks, we propose a novel Green DataPath architecture, where the dynamic voltage and frequency scaling (DVFS) power ...
A TCAM-based flow table is power-hungry hardware that can provide high-speed lookup operations for packet switching networks. ...
The frequency/voltage configuration of a TCAM chip can be tuned adaptively. ...
doi:10.1109/mcom.2016.1600067cm
fatcat:siarrbzkg5anjgvheb3omlyxq4
Runtime adaptive Dynamic Voltage Frequency Scaling technique for reducing the power consumption in Multi Processor System On Chip
2019
JOURNAL OF MECHANICS OF CONTINUA AND MATHEMATICAL SCIENCES
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In VLSI due to recent advancements , there is a need for integration of multiple processors into a single chip. System on chip (Soc) and MPSoc consist of many processors on a single dye. ...
This paper mainly focuses on Various power optimization techniques for reducing the power utilization in network . ...
[XXIX] has presented a work based on per-core DVFS architecture for on chip network. In this work voltage supply is adjusted dynamically at a very Kees Goossens et al. ...
doi:10.26782/jmcms.spl.2019.08.00053
fatcat:6cgdpzgkrvdxzovced3okxlecu
Voltage Controlled Oscillators for 40Gbit/s Cascaded Bit-Interleaving PON
2015
2015 Advances in Wireless and Optical Communications (RTUWO)
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This paper presents the VCOs designed for the CABINET chip, an implementation of a CBI-PON network device, allowing clock-and-data recovery for 40 Gbit/s, 10 Gbit/s and 2.5 Gbit/s line rates. ...
flexible dynamic bandwidth allocation scheme. ...
As for the 40 Gbit/s case, it is a resistively loaded common However, fine tuning is not implemented on the delay cell level, but on the level of the core VCO. ...
doi:10.1109/rtuwo.2015.7365730
fatcat:uqwxwsn66jfeji5xoyfn7whwpu
Test Procedures for Synchronized Oscillators Network CMOS VLSI Chip
2015
International Journal of Electronics and Telecommunications
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The paper presents test procedures designed for application-specific integrated circuit (ASIC) CMOS VLSI chip prototype that implements a synchronized oscillator neural network with a matrix size of 32 ...
×32 for object detecting in binary images. ...
Fig. 13 . 13 Control signals required for input image loading into a chip with oscillators frequency tuning. ...
doi:10.1515/eletel-2015-0013
fatcat:oqy5wl4wirdxhfk3fxecdmx3cu
Tribeca
2009
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture - Micro-42
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While a processor designed for worst-case conditions might only be capable of a frequency that is 75% of an ideal processor with no parameter variations, we show that a fine-grained global frequency tuning ...
This paper explores the powerperformance efficiency gains that result from designing for typical conditions while dynamically tuning frequency and voltage to accommodate the runtime behavior of workloads ...
The ideal dynamic-voltage and frequency scaling curve has been plotted for a median chip with no tuning mechanism and for the same chip assuming a local voltage-tuning mechanism. ...
doi:10.1145/1669112.1669168
dblp:conf/micro/GuptaRBWB09
fatcat:iqgwublgtfh4lec6onqzd35jk4
Programmable photonic signal processor chip for radiofrequency applications
2015
Optica
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We use a grid of tunable Mach-Zehnder couplers interconnected in a two-dimensional mesh network, each working as a photonic processing unit. ...
Integrated microwave photonics, an emerging technology combining radio frequency (RF) engineering and integrated photonics, has great potential to be adopted for wideband analog processing applications ...
For one thing, increasing the network dimension means enlarging the chip area. ...
doi:10.1364/optica.2.000854
fatcat:v6og4pj7irfzjmbzzmsbjvnp4q
Programmable photonic signal processor chip for radiofrequency applications
[article]
2015
arXiv
pre-print
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For the abstract, please see the submitted article. ...
Unlike the operation for the filter center frequency tuning, Δf 1 and Δf 2 (as referred to in Figure 3 ) are shifted independently in this case and the frequency difference between them Δf RF = |Δf 1 ...
On this chip, the phase shifters are found with a full tuning range of 0 to 2π; the power coupling coefficient of the MZ couplers can be tuned very close to the ideal case, i.e., tunable between 0 and ...
arXiv:1505.00094v1
fatcat:z7zmndrbgnds5lvpiygckmd7ay
Active deskew in injection-locked clocking
2008
2008 IEEE Custom Integrated Circuits Conference
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A test chip was fabricated in a standard 0.18 m digital CMOS process to demonstrate this new technique. ...
This paper presents an injection-locked clock (ILC) distribution system with a new active deskew mechanism based on the built-in phase tuning of injection-locked oscillators (ILO). ...
Chatterjee, A. Bahai, P. Holloway, M. Bohsali, J. Yu, A. Shah, V. Abellera, P. Misich, and J. Wan of National Semiconductor for their support in chip fabrication. We also thank P.J. ...
doi:10.1109/cicc.2008.4672148
dblp:conf/cicc/ZhangCW08
fatcat:zcxkuz2btjhzthnvk4bisj24jq
A clock distribution network for microprocessors
2001
IEEE Journal of Solid-State Circuits
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A new tuning method was required to efficiently tune such a large strongly connected interconnect network consisting of up to 6 m of wire and modeled with 50 000 resistors, capacitors, and inductors. ...
He holds four patents, has written 15 papers, and has given several invited talks and tutorials on high-frequency on-chip interconnects. Dr. ...
Anderson of the IBM Enterprise Systems Group, for many valuable interactions. ...
doi:10.1109/4.918917
fatcat:c2564ix42rcfxo5bez7xqupoqe
Tuning-free controller to accurately regulate flow rates in a microfluidic network
2016
Scientific Reports
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For this reason, some lab-on-a-chip devices adopt a feedback control scheme to achieve high precision in flow control. ...
The capability of the control algorithm can be used not only in high-precision flow regulation in the presence of disturbance, but in some useful functions for lab-on-a-chip devices such as regulation ...
In this case, tuning is not practical; this is the main disadvantage of using a PID controller for a microfluidic network. ...
doi:10.1038/srep23273
pmid:26987587
pmcid:PMC4796872
fatcat:74xp2jyaj5dspklux55pjd227e
A high-dynamic-range integrated continuous-time bandpass filter
1992
IEEE Journal of Solid-State Circuits
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The filter features an optimized dynamic range, a large tuning range, and a small occupied chip area of 0.25 mm2 owing to very simple circuitry. ...
Measurements show a very accurate realization of the desired transfer function, a high dynamic range of 62 dB, and a tuning range from 50 to 200 kHz. ...
Let s" be the (dimensionless) Laplace operator for the normalized low-pass equivalent case, and s the Laplace operator for the bandpass case (with the dimension of a frequency). ...
doi:10.1109/4.165343
fatcat:j6vmifimwzdlzpa3nvnet2z7q4
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