Filters








451 Hits in 3.3 sec

A cache topology-aware multi-query scheduler for multicore architectures

Umut Orhan, Wei Ding, Praveen Yedlapalli, Mahmut Kandemir, Ozcan Ozturk
2014 2014 IEEE International Symposium on Workload Characterization (IISWC)  
In Figure 1 , we give the high-level view of our automated approach to cache topology aware query scheduling. architecture.  ...  Fig. 1: High level sketch of our cache topology-aware query scheduling approach.  ... 
doi:10.1109/iiswc.2014.6983047 dblp:conf/iiswc/OrhanDYKO14 fatcat:4koxvgoggrgvth4fxikeo4mr4u

Cache Hierarchy-Aware Query Mapping on Emerging Multicore Architectures

Ozcan Ozturk, Umut Orhan, Wei Ding, Praveen Yedlapalli, Mahmut Taylan Kandemir
2017 IEEE transactions on computers  
Our proposed scheme distributes a given batch of queries across the cores of a target multicore architecture based on the affinity relations among the queries.  ...  Each domain affinity in this context corresponds to a cache structure bounded by a particular level of the cache hierarchy.  ...  ACKNOWLEDGMENTS A preliminary 2-page version of this paper appears in the Proceedings of 2014 IEEE International Symposium on Workload Characterization (IISWC) [27] . This work has been done when U.  ... 
doi:10.1109/tc.2016.2605682 fatcat:fdfe4mhddrhyfk4isdwak2tkd4

A User-Level NUMA-Aware Scheduler for Optimizing Virtual Machine Performance [chapter]

Yuxia Cheng, Wenzhi Chen, Xiao Chen, Bin Xu, Shaoyu Zhang
2013 Lecture Notes in Computer Science  
Experimental results show that our NUMA-aware virtual machine scheduling algorithm is able to improve VM performance by up to 23.4% compared with the default CFS (Completely Fair Scheduler) scheduler used  ...  In this paper, we propose a "Best NUMA Node" based virtual machine scheduling algorithm and implement it in a user-level scheduler that can periodically adjust the placement of VMs running on NUMA systems  ...  [14] presented a method that allows the guest OS to query the VMM via para-virtualized hypercalls about the NUMA topology.  ... 
doi:10.1007/978-3-642-45293-2_3 fatcat:4pg43s4yy5gb7fv5ilsn75eqfi

Efficient Query Processing on Many-core Architectures

Xuntao Cheng, Bingsheng He, Mian Lu, Chiew Tong Lau, Huynh Phung Huynh, Rick Siow Mong Goh
2016 Proceedings of the 2016 International Conference on Management of Data - SIGMOD '16  
In PhiDB, we apply Xeon Phi aware optimizations on query operators to exploit hardware features of Xeon Phi, and design a heuristic algorithm to schedule the concurrent execution of query operators for  ...  With the trend towards many-core architectures, query operator optimizations, and efficient query scheduling on such many-core architectures remain as challenging issues.  ...  INTRODUCTION Computer architectures have been evolving from multicore processors to many-core processors with emerging architectural features.  ... 
doi:10.1145/2882903.2899407 dblp:conf/sigmod/ChengHLLHG16 fatcat:ocxssv5zpjbdfo5golx23gople

Locality Aware Task Scheduling in Parallel Data Stream Processing [chapter]

Zbyněk Falt, Martin Kruliš, David Bednárek, Jakub Yaghob, Filip Zavoral
2015 Studies in Computational Intelligence  
The multiprocessor systems and CPU architecture of the day become quite complex, which makes the task scheduling a challenging problem.  ...  In this paper, we propose a novel task scheduling strategy for parallel data stream systems, that reflects many technical issues of the current hardware.  ...  The multi-query tests (Figure 8 ) emphasize the benefits of NUMA aware scheduling along with NUMA aware memory allocation.  ... 
doi:10.1007/978-3-319-10422-5_35 fatcat:56g7pv2m3faybftgshjicfxbrm

TACO: A Scheduling Scheme for Parallel Applications on Multicore Architectures

Jan H. Schönherr, Ben Juurlink, Jan Richling
2014 Scientific Programming  
Additionally, TACO is conceptually compatible with contention-aware scheduling strategies. We find that topology-awareness increases performance for all evaluated workloads.  ...  We propose TACO, a topology-aware scheduling scheme that combines equipartitioning and coscheduling, which does not suffer from the drawbacks of the individual concepts.  ...  Basis In order to create a scheduling scheme for modern multicore architectures, we combine the ideas of equipartitioning and coscheduling.  ... 
doi:10.1155/2014/423084 fatcat:6cuvj4r4ovhrvml3hy2yvpqf2q

Toward Efficient In-memory Data Analytics on NUMA Systems [article]

Puya Memarzia, Suprio Ray, Virendra C Bhavsar
2020 arXiv   pre-print
A key drawback of NUMA architectures is that many existing software solutions are not aware of the underlying NUMA topology and thus do not take full advantage of the hardware.  ...  Data analytics systems commonly utilize in-memory query processing techniques to achieve better throughput and lower latency.  ...  ACKNOWLEDGEMENTS We would like to thank Kenneth Kent and Aaron Graham from IBM CASA and Serguei Vassiliev and Kaizaad Bilimorya from Compute Canada, for providing access to Machine B and Machine C respectively  ... 
arXiv:1908.01860v3 fatcat:3ri4vadygzce5ao5dslmakn7zm

Databases and hardware

Anastasia Ailamaki
2015 Proceedings of the VLDB Endowment  
Fast query and transaction processing is the goal of 40 years of database research and the reason of existence for many new database system architectures.  ...  the interaction between the database software and underlying hardware and show that, as application and microarchitecture roadmaps evolve, the effort of maintaining smooth collaboration blossoms into a  ...  Moreover, ADDICT exploits the aggregate L1 instruction cache capacity of the multicore architectures.  ... 
doi:10.14778/2824032.2824142 fatcat:ugl7ujexjng57fqbebzt3oecre

ForestGOMP: An Efficient OpenMP Environment for NUMA Architectures

François Broquedis, Nathalie Furmento, Brice Goglin, Pierre-André Wacrenier, Raymond Namyst
2010 International journal of parallel programming  
Our runtime, which is based on a multi-level thread scheduler combined with a NUMAaware memory manager, converts this information into scheduling hints related to threadmemory affinity issues.  ...  Exploiting the full computational power of current hierarchical multiprocessor machines requires a very careful distribution of threads and data among the underlying non-uniform architecture so as to avoid  ...  Therefore, we introduce a multi-level thread scheduler combined with a NUMA-aware memory manager.  ... 
doi:10.1007/s10766-010-0136-3 fatcat:g2vajlq53ba4xeq2xjkfdriesy

2020 Index IEEE Transactions on Parallel and Distributed Systems Vol. 31

2021 IEEE Transactions on Parallel and Distributed Systems  
., +, TPDS Jan. 2019 79-92 Resource-Aware Scheduling for Dependable Multicore Real-Time Systems: Utilization Bound and Partitioning Algorithm.  ...  ., +, TPDS July 2019 1449-1463 Dependency-Aware Network Adaptive Scheduling of Data-Intensive Paral-Efficient Data Placement and Replication for QoS-Aware Approximate Query Evaluation of Big Data Analytics  ... 
doi:10.1109/tpds.2020.3033655 fatcat:cpeatdjlpzhqdersvsk5nmzjkm

Topology-aware equipartitioning with coscheduling on multicore systems

Jan H. Schonherr, Ben Juurlink, Jan Richling
2013 2013 IEEE 6th International Workshop on Multi-/Many-core Computing Systems (MuCoCoS)  
We propose a topology-aware scheduling scheme that combines equipartitioning and coscheduling.  ...  Combined with the ever increasing complexity of multicore architectures, this results in a scheduling problem that is different from what it has been, because features such as non-uniform memory access  ...  Basis In order to create an equipartitioning scheme for modern multicore architectures, we combine the idea of equipartitioning with coscheduling.  ... 
doi:10.1109/mucocos.2013.6633602 fatcat:7bezaxuktfb7tdmbwtk36vf5ba

2014 Index IEEE Transactions on Parallel and Distributed Systems Vol. 25

2015 IEEE Transactions on Parallel and Distributed Systems  
., +, TPDS June 2014 1638-1647 CPU Scheduling for Power/Energy Management on Multicore Processors Using Cache Miss and Context Switch Data. Datta, A.  ...  Feliu, Josue, +, TPDS March 2014 581-590 CPU Scheduling for Power/Energy Management on Multicore Processors Using Cache Miss and Context Switch Data. Datta, A.  ...  ., +, TPDS Aug. 2014 2840 -2850 Energy and Network Aware Workload Management for Sustainable Data Centers with Thermal Storage. 2030 -2042 Hyperbolic Utilization Bounds for Rate Monotonic Scheduling  ... 
doi:10.1109/tpds.2014.2371591 fatcat:qxyljogalrbfficryqjowgv3je

A PetriNet mechanism for OLAP in NUMA

Simone Dominico, Eduardo Cunha de Almeida, Jorge Augusto Meira
2017 Proceedings of the 13th International Workshop on Data Management on New Hardware - DAMON '17  
CCS CONCEPTS •Computer systems organization →Multicore architectures; •Information systems →Data management systems; KEYWORDS Multi-core CPUs; OLAP; Abstract Model; NUMA  ...  In this paper we present a PetriNet mechanism that represents the load of the database workers for dynamically computing and allocating the local optimum number of CPU cores to tackle such load.  ...  MCC-DB classi es queries in cache-sensitive and cacheinsensitive to feed the query execution scheduler.  ... 
doi:10.1145/3076113.3076121 dblp:conf/damon/DominicoAM17 fatcat:6ovugfeibjbbfl5g6mhgchvfti

Abstracting Multi-Core Topologies with MCTOP

Georgios Chatzopoulos, Rachid Guerraoui, Tim Harris, Vasileios Trigonakis
2017 Proceedings of the Twelfth European Conference on Computer Systems - EuroSys '17  
These libraries offer a topology representation of multi-cores, as well as a companion interface for placing threads (and data).  ...  We illustrate several such policies through four examples: (i-ii) thread placement in OpenMP and in a MapReduce library, (iii) a topology-aware mergesort algorithm, as well as (iv) automatic backoff schemes  ...  Acknowledgments We wish to thank our shepherd, Jean-Pierre Lozi, and the anonymous reviewers for their fruitful comments on improving the paper.  ... 
doi:10.1145/3064176.3064194 dblp:conf/eurosys/ChatzopoulosG0T17 fatcat:xoxdudvpx5dcxph5lnkokoe2yy

NUMA-Aware DGEMM Based on 64-Bit ARMv8 Multicore Processors Architecture

Wei Zhang, Zihao Jiang, Zhiguang Chen, Nong Xiao, Yang Ou
2021 Electronics  
This poses a challenge to develop high-performance DGEMM on multi-NUMA architecture. We present a NUMA-aware method to reduce the number of cross-die and cross-chip memory access events.  ...  We have implemented NUMA-aware DGEMM in the OpenBLAS and evaluated it on a dual-socket server with 48-core processors based on the Kunpeng920 architecture.  ...  Acknowledgments: The authors thank ZhiGuang Chen and Nong Xiao for their guidance and the server provided by Pengcheng Labs. Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/electronics10161984 fatcat:mkevjicswjfpzcdrtsfarp2dnq
« Previous Showing results 1 — 15 out of 451 results