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A buffer cache management scheme exploiting both temporal and spatial localities

Xiaoning Ding, Song Jiang, Feng Chen
2007 ACM Transactions on Storage  
To address this problem, we propose a scheme called DULO (DUal LOcality) which exploits both temporal and spatial localities in the buffer cache management.  ...  Unfortunately, spatial locality of cached blocks is largely ignored, and only temporal locality is considered in current system buffer cache managements.  ...  ACKNOWLEDGMENTS We would like to thank Professor Xiaodong Zhang for his advice, suggestions, and support to this work.  ... 
doi:10.1145/1242520.1242522 fatcat:ikvgdy2jb5ai3pxoy4nxsicm2m

Improving data cache performance with integrated use of split caches, victim cache and stream buffers

Afrin Naz, Mehran Rezaei, Krishna Kavi, Philip Sweany
2005 SIGARCH Computer Architecture News  
In our prior work we explored a cache organization providing architectural support for distinguishing between memory references that exhibit spatial and temporal locality and mapping them to separate caches  ...  In this paper, we investigate the interaction between three established methods, split cache, victim cache and stream buffer.  ...  This work is supported in part by a NSF grant ITR-0081214 (subcontract from Washington University in St. Louis).  ... 
doi:10.1145/1101868.1101876 fatcat:rdcgf6yxcbavppdyjbljkdecli

Improving data cache performance with integrated use of split caches, victim cache and stream buffers

Afrin Naz, Mehran Rezaei, Krishna Kavi, Philip Sweany
2004 Proceedings of the 2004 workshop on MEmory performance DEaling with Applications , systems and architecture - MEDEA '04  
In our prior work we explored a cache organization providing architectural support for distinguishing between memory references that exhibit spatial and temporal locality and mapping them to separate caches  ...  In this paper, we investigate the interaction between three established methods, split cache, victim cache and stream buffer.  ...  This work is supported in part by a NSF grant ITR-0081214 (subcontract from Washington University in St. Louis).  ... 
doi:10.1145/1152922.1101876 fatcat:e5hol53y2zgfrna3os2stzoihe

BPAC: An adaptive write buffer management scheme for flash-based Solid State Drives

Guanying Wu, Ben Eckart, Xubin He
2010 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST)  
We develop a hybrid page/block architecture along with an advanced replacement policy, called BPAC, or Block-Page Adaptive Cache, to exploit both temporal and spatial locality.  ...  Our technique involves adaptively partitioning the SSD on-disk cache to separately hold pages with high temporal locality in a page list and clusters of pages with low temporal but high spatial locality  ...  Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.  ... 
doi:10.1109/msst.2010.5496998 dblp:conf/mss/WuEH10 fatcat:rmzgct4z7fckhgj7dbr2xeellq

An adaptive write buffer management scheme for flash-based SSDs

Guanying Wu, Xubin He, Ben Eckart
2012 ACM Transactions on Storage  
architecture along with an advanced replacement policy, called BPAC, or Block-Page Adaptive Cache, to exploit both temporal and spatial locality.  ...  Our technique involves adaptively partitioning the SSD on-disk cache to separately hold pages with high temporal locality in a page list and clusters of pages with low temporal but high spatial locality  ...  CONCLUSION In this article, we present BPAC, an adaptive flash-aware write cache that minimizes evictions by exploiting both spatial and temporal locality.  ... 
doi:10.1145/2093139.2093140 fatcat:44e34txgzja5pd6t3iu3wjuhau

An intelligent cache system with hardware prefetching for high performance

Jung-Hoon Lee, Seh-woong Jeong, Shin-Dug Kim, C.C. Weems
2003 IEEE transactions on computers  
., a small block size to exploit temporal locality and a large block size that is a multiple of the small block size to exploit spatial locality.  ...  The small block size exploits temporal locality and the large block size exploits spatial locality. Small blocks are first loaded as part of larger blocks that are fetched into the spatial buffer.  ... 
doi:10.1109/tc.2003.1197127 fatcat:lixaulhl25eqnpwbdm6m5bvi5m

Spatial Locality-Aware Cache Partitioning for Effective Cache Sharing

Saurabh Gupta, Huiyang Zhou
2015 2015 44th International Conference on Parallel Processing  
To leverage spatial locality for cache partitioning effectively, we first propose a simple yet effective mechanism to measure both spatial and temporal locality at run-time.  ...  Keywords -shared last level cache; cache partitioning; spatial locality; cache management; high bandwidth memory.  ...  This research is supported by an NSF grant CCF-1216569, a research fund from Intel Corporation, and a Chinese research program "introducing talents of discipline to universities B13043".  ... 
doi:10.1109/icpp.2015.24 dblp:conf/icpp/GuptaZ15 fatcat:yfywugggwjfuzm5lfvghodwvda

RFFE: A Buffer Cache Management Algorithm for Flash-Memory-Based SSD to Improve Write Performance

Arul Selvan Ramasamy, Porkumaran Karantharaj
2015 Canadian journal of electrical and computer engineering  
Many of the previously proposed write buffer cache management algorithms concentrate on improving the random write performance either by reordering the writes, addressing the temporal locality or evicting  ...  An efficient RFLRU implementation is developed and tested in a trace driven simulation environment and compared to the previously proposed LRU FAST, BPLRU and REF buffer management schemes.  ...  It is of advantage to incorporate a write-back cache, building on principles used in conventional file system cache to address the temporal and spatial locality in the write workload.  ... 
doi:10.1109/cjece.2015.2431745 fatcat:lqo2rzfnfjgjxn7etgyui4hkea

STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches

Dongyuan Zhan, Hong Jiang, Sharad C. Seth
2010 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture  
Therefore, we propose a novel adaptive scheme, called STEM, which concurrently and dynamically manages both spatial and temporal dimensions of capacity demands at the set level.  ...  In the proposed scheme, a set-level monitor captures the temporal and spatial capacity demands of individual working sets and judiciously pairs off sets with complementary capacity demands so that the  ...  We also greatly appreciate the constructive comments and suggestions from the anonymous reviewers.  ... 
doi:10.1109/micro.2010.31 dblp:conf/micro/ZhanJS10 fatcat:gaure3r7cvhsvcgbyv7ct2bx7i

Page 615 of IEEE Transactions on Computers Vol. 52, Issue 5 [page]

2003 IEEE Transactions on Computers  
73, 1992 temporal locality and a fully associative spatial buffer with [3] W.  ...  Lee, and $.D. Kim, “A New Cache Architecture Based memory access time of the SMI cache for a given cache on Temporal and Spatial Locality,” J.  ... 

Exploring the performance of split data cache schemes on superscalar processors and symmetric multiprocessors

J. Sahuquillo, S. Petit, A. Pont, V. Milutinović
2005 Journal of systems architecture  
In this sense, the cache schemes that propose a better exploitation of data locality (bypassing schemes, prefetching techniques, victim caches, etc.) are a good example.  ...  This paper presents a data cache scheme called filter cache that splits the first level data cache into two independent organizations, and its performance is compared with two other proposals appearing  ...  The spatial cache exploits both types of spatial locality (only spatial, or both spatial and temporal).  ... 
doi:10.1016/j.sysarc.2004.12.002 fatcat:4jdsqp6ipzc6tdshyk7y6cxg74

Monte Carlo Based Ray Tracing in CPU-GPU Heterogeneous Systems and Applications in Radiation Therapy

Kai Xiao, Danny Z. Chen, X. Sharon Hu, Bo Zhou
2015 Proceedings of the 24th International Symposium on High-Performance Parallel and Distributed Computing - HPDC '15  
LE-MCBRT is based on task partitioning and scheduling, which enhances both the spatial and temporal data locality by organizing random rays into coherent groups.  ...  We also develop a CPU-GPU pipeline scheme to reduce the overhead in such ray organization process.  ...  Acknowledgments This research was supported in part by NSF under Grant CCF-1217906 and by a research contract from the Sandia National Laboratories.  ... 
doi:10.1145/2749246.2749271 dblp:conf/hpdc/XiaoCHZ15 fatcat:nmozvxvsyrfbpljgfgmsbchefm

Hardware Prediction for Data Coherency of Scientific Codes on DSM

JT. Acquaviva, W. Jalby
2000 ACM/IEEE SC 2000 Conference (SC'00)  
Once a stream is detected at a loop level, regularity of data access can be exploited at the loop level (spatial locality) but also between loops (temporal locality).  ...  We present a hardware mechanism capable of detecting and exploiting efficiently these regular patterns.  ...  Acknowledgements Ekanadham Kattamuri from IBM for his helpful advises and comments on the IBM PRISM simulator.  ... 
doi:10.1109/sc.2000.10037 dblp:conf/sc/AcquavivaJ00 fatcat:qzsqb3s2uvc4zic63zpdrjtel4

CrypTag: Thwarting Physical and Logical Memory Vulnerabilities using Cryptographically Colored Memory [article]

Pascal Nasahl, Robert Schilling, Mario Werner, Jan Hoogerbrugge, Marcel Medwed, Stefan Mangard
2020 arXiv   pre-print
Memory vulnerabilities are a major threat to many computing systems. To effectively thwart spatial and temporal memory vulnerabilities, full logical memory safety is required.  ...  Surprisingly, the combination of both, logical and physical memory safety, has not yet been extensively studied in previous research, and a naive combination of both security strategies would accumulate  ...  This project has received funding from the European Research Council (ERC) under the European Union's Horizon 2020 research and innovation programme (grant agreement No 681402) and by the Austrian Research  ... 
arXiv:2012.06761v1 fatcat:afol6cxu6ffppmknlvtogckwpq

3.5-D Blocking Optimization for Stencil Computations on Modern CPUs and GPUs

Anthony Nguyen, Nadathur Satish, Jatin Chhugani, Changkyu Kim, Pradeep Dubey
2010 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis  
We present a novel 3.5D-blocking algorithm that performs 2.5D-spatial and temporal blocking of the input grid into on-chip memory for both CPUs and GPUs.  ...  Stencil computation sweeps over a spatial grid over multiple time steps to perform nearest-neighbor computations.  ...  /spatial blocking and both temporal and spatial blocking (3.5D blocking).  ... 
doi:10.1109/sc.2010.2 dblp:conf/sc/NguyenSCKD10 fatcat:c3p2ydqkejh7la6dua663awic4
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