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A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{\min}$ Lowering Techniques and Deep Sleep Mode

Tae-Hyoung Kim, Jason Liu, Chris H. Kim
2009 IEEE Journal of Solid-State Circuits  
A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a read current at subthreshold supply voltages.  ...  A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process.  ...  In this work, we propose a marginal bitline leakage compensation (MBLC) technique suitable for bitline leakage compensation in ultra-low-voltage SRAMs.  ... 
doi:10.1109/jssc.2009.2020201 fatcat:ydvsacuavbbsbjbt7sbaz7thwu

Sensing Margin Enhancement Techniques for Ultra-Low-Voltage SRAMs Utilizing a Bitline-Boosting Current and Equalized Bitline Leakage

Anh Tuan Do, Truc Quynh Nguyen, Kiat Seng Yeo, Tony Tae-Hyoung Kim
2012 IEEE Transactions on Circuits and Systems - II - Express Briefs  
A small bitline sensing margin is one of the most challenging design obstacles for reliable ultra-low-voltage static random access memory (SRAM) implementation.  ...  The proposed bitline-boosting current scheme improves the bitline sensing margin at a given bitline configuration. The bitline sensing margin can be further augmented by equalizing bitline leakage.  ...  BITLINE SENSING CHALLENGES IN CONVENTIONAL ULTRA-LOW-VOLTAGE SRAMs Decoupled 8T SRAM cells have been widely accepted in ultra-low-power and low-voltage SRAMs due to the significantly improved stability  ... 
doi:10.1109/tcsii.2012.2231014 fatcat:vvzqk7axjfc5fbqqkdb5mkdq54

A fully-differential subthreshold SRAM cell with auto-compensation

Mu-Tien Chang, Wei Hwang
2008 APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems  
SRAM cell stability is a major challenge in subthreshold SRAM design. In this paper, a robust, fullydifferential subthreshold 10-transistors SRAM cell with autocompensation is proposed.  ...  With the auto-compensation mechanism, the proposed cell exhibits better hold static noise margin (SNM).  ...  As a result, the proposed AC cell has higher potential for ultra-low voltage data retention in future nanoscaled technologies. V.  ... 
doi:10.1109/apccas.2008.4746384 dblp:conf/apccas/ChangH08 fatcat:fobd4h2hszgzfleopbnyw5lofe

A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme

Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim
2007 Digest of technical papers / IEEE International Solid-State Circuits Conference  
for write margin improvement, (iii) eliminating data-dependent bitline leakage to enable long bitlines, (iv) virtual ground replica scheme for improved bitline sensing margin, (v) writeback scheme for  ...  Robust high-density subthreshold SRAMs are indispensable for emerging ultra-low power applications such as implantable devices, medical instruments, and wireless sensor networks.  ...  Fisher for the assistance with chip fabrication and lab equipments. 1-4244-0852-0/07/$25.00 ©2007 IEEE.  ... 
doi:10.1109/isscc.2007.373428 dblp:conf/isscc/KimLKK07 fatcat:e37jornavnanjlmxlidbw3exou

Low Computing Leakage, Wide-Swing Output Compensation Circuit for Linearity Improvement in SRAM Multi-Row Read Computing-in-Memory

Zupei Gu, Huidong Zhao, Xiaoqin Wang, Shushan Qiao, Yumei Zhou
2022 Electronics  
In this study, a low computing leakage, wide-swing output compensation circuit is proposed for linearity improvement in such circumstances.  ...  The proposed compensation circuit is composed of a current competition circuit (as dynamic feedback of the bitline discharge current), a current mirror (to separate the result capacitor and provide charge  ...  Lin in [12] proposed a current-mirrorbased compensation circuit which provided an extra charge current for the bitline when the voltage is low.  ... 
doi:10.3390/electronics11091376 fatcat:jqjp6aznbza6zmuh7hdq4xzhyi

A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement

Qi Li, Bo Wang, Tony T. Kim
2012 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC)  
A 5.61 pJ, 16 kb 9T SRAM is implemented in 65nm CMOS technology. A single-ended equalized bitline scheme is proposed to improve both read bitline voltage swing and sensing timing window.  ...  A fast local write-back allows the half-select-free write operation without performance degradation. The test chip shows a minimum operating voltage of 0.24V and a minimum energy of 5.61pJ at 0.3V. I.  ...  Write-back schemes have been utilized in many low-voltage SRAMs for improving the stability of half-selected cells by using an additional clock cycle.  ... 
doi:10.1109/essderc.2012.6343368 dblp:conf/essderc/LiWK12 fatcat:drajcn5sena67mbamf3mc5s7mi

A 32kb 9T SRAM with PVT-tracking read margin enhancement for ultra-low voltage operation

Anh-Tuan Do, Kiat-Seng Yeo, Tony Tae-Hyoung Kim
2015 2015 IEEE International Symposium on Circuits and Systems (ISCAS)  
Diminishing bitline sensing margin at low voltage condition is one of the most challenging design obstacles for reliable SRAM implementation in nano-scale CMOS technologies.  ...  Furthermore, a 9T SRAM cell is utilized to ensure that bitline leakage is data-independent.  ...  Therefore, leakage-aware bitline structure design is highly required in low-voltage SRAM designs.  ... 
doi:10.1109/iscas.2015.7169206 dblp:conf/iscas/DoYK15 fatcat:2vhwqlpe3baivbf54e3vvg3bue

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim
2008 IEEE Journal of Solid-State Circuits  
Fisher for assistance with chip fabrication and laboratory equipment.  ...  (a) Block diagram for test circuit implemented. (b) Measured row decoding path delay improvement. A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing I.  ...  (b) Proposed scheme eliminating data-dependent bitline leakage current. Fig. 10 . 10 VGND replica scheme for ideal bitline sensing margin. (a) Bitline sensing margin comparison of read buffers.  ... 
doi:10.1109/jssc.2007.914328 fatcat:dart62szqrflzcx5rkkb2dzsb4

A robust ultra-low power asynchronous FIFO memory with self-adaptive power control

Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
2008 2008 IEEE International SOC Conference  
Moreover, with the proposed dual-V T 7T SRAM cell, the FIFO memory has improved stability under ultra-low voltage supply.  ...  First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed.  ...  Fig. 5 (a) shows that the proposed scheme exhibits better write ability under low supply voltage.  ... 
doi:10.1109/socc.2008.4641505 dblp:conf/socc/ChangHH08 fatcat:5e76xkolp5djfbm4zim2jpjvi4

Maximization of SRAM energy efficiency utilizing MTCMOS technology

Bo Wang, Jun Zhou, Tony T. Kim
2012 2012 4th Asia Symposium on Quality Electronic Design (ASQED)  
However, at ultra-low supply voltage levels, higher-V th devices can retard or nullify energy efficiency due to substantially slower write speed than read.  ...  Higher-V th devices in the cross-coupled latches and the write access transistors, and lower-V th devices in the read ports are preferred for reducing leakage current without sacrificing performance.  ...  Bitline leakage reduction [5] , [6] , bitline equalization [7] , [8] , bitline leakage compensation [9] , and bitline sensing with redundant sense amplifiers [10] have been published for improving  ... 
doi:10.1109/acqed.2012.6320472 fatcat:gumz2oj7orc3hojz3hlpg4g4ci

SRAM devices and circuits optimization toward energy efficiency in multi-Vth CMOS

Bo Wang, Jun Zhou, Tony Tae-Hyoung Kim
2015 Microelectronics Journal  
This paper presents SRAM energy analysis utilizing multi-threshold (multi-V th ) voltage devices and various circuit techniques for power reduction and performance improvement, and suggests optimal device  ...  Due to high computing capability requirements in such applications, SRAMs play a critical role in energy consumption.  ...  A. Do (NTU, Singapore) for their technical support and input.  ... 
doi:10.1016/j.mejo.2014.12.003 fatcat:t3ecuii6rvdwlpihe3vn3zxb7u

A robust, subthreshold 12T SRAM bitcell with BL leakage compensation and bit-interleaving capability

De-bin Kong, Jia Yuan, Shan-shan Li, Heng You, Shu-shan Qiao
2018 IEICE Electronics Express  
This paper presents a novel 12T SRAM bitcell suitable for subthreshold operation.  ...  Multi-threshold voltage metric is utilized to improve writability and leakage consumption.  ...  robust, multi-V th 12T SRAM bitcell with bitline leakage compensation and bit-interleaving capability.  ... 
doi:10.1587/elex.15.20180758 fatcat:vwalhdmfi5fx5jx72jhqircvmi

A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS

Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy
2008 Digest of technical papers / IEEE International Solid-State Circuits Conference  
In single-ended READ structure, leakage makes it difficult to distinguish a logic high and low from the developed bitline voltage [3] .  ...  Since a differential read does not solely depend on the trip voltage of an inverter, it is more tolerant to bitline leakage noise.  ...  We thank Keejong Kim for integration of the design into a multi-project chip; Hyun-Joong Kim for helping wire-bonding; and Samsung Scholarship Foundation.  ... 
doi:10.1109/isscc.2008.4523220 dblp:conf/isscc/ChangKPR08 fatcat:fvahkiccnnec3iudmp3syagr6q

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy
2009 IEEE Journal of Solid-State Circuits  
In single-ended READ structure, leakage makes it difficult to distinguish a logic high and low from the developed bitline voltage [3] .  ...  Since a differential read does not solely depend on the trip voltage of an inverter, it is more tolerant to bitline leakage noise.  ...  We thank Keejong Kim for integration of the design into a multi-project chip; Hyun-Joong Kim for helping wire-bonding; and Samsung Scholarship Foundation.  ... 
doi:10.1109/jssc.2008.2011972 fatcat:r2axxo4h6jaztmiwlivskgkho4

Hybridization of CMOS With CNT-Based Nano-Electromechanical Switch for Low Leakage and Robust Circuit Design

Rajat Subhra Chakraborty, Seetharam Narasimhan, Swarup Bhunia
2007 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Due to the unique electromechanical properties of CNTs, these switches have high current-carrying capacity, extremely low leakage current, and low operating voltages.  ...  Simulation results for a set of benchmark circuits show that we can obtain several orders of magnitude improvement in leakage saving in logic circuits at iso-performance compared to existing multi-threshold  ...  In [26] , a bitline "compensation" scheme has been proposed that measures the bitline leakage in precharge phase, and then injects the same amount of current in the evaluate phase to "compensate" for  ... 
doi:10.1109/tcsi.2007.907828 fatcat:phpvg5sz5ndsje4fj6rkytgrva
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