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A versatile and scalable digit-serial/parallel multiplier architecture for finite fields GF(2/sup m/)

M. Hutter, J. Grossschadl, G.-A. Kamendje
Proceedings ITCC 2003. International Conference on Information Technology: Coding and Computing  
We present an architecture for digit-serial multiplication in finite fields GF(2 m ) with applications to cryptography.  ...  An M-bit multiplier works with arbitrary irreducible polynomials and can be used for any binary field of order 2 m ≤ 2 M .  ...  In order to be appropriate for various different applications, a finite field multiplier for smart cards needs to be versatile and scalable.  ... 
doi:10.1109/itcc.2003.1197615 dblp:conf/itcc/HutterGK03 fatcat:3elrgp5oajhxzg4zmnd3cqudve