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A Verification Approach for GALS Integration of Synchronous Components

F. Doucet, M. Menarini, I.H. Krüger, R. Gupta, J.-P. Talpin
2006 Electronical Notes in Theoretical Computer Science  
Starting with modules described in Signal synchronous programming language, we present an approach to verification of GALS systems.  ...  This allows us to achieve globally asynchronous composition (Promela) of locally synchronous components (Signal).  ...  We are grateful to the anonymous reviewers for their insightful comments.  ... 
doi:10.1016/j.entcs.2005.05.038 fatcat:3qpjl7umezakhhjrwvxbdsupmm

Asynchronous-Channels and Time-Domains Extending Petri Nets for GALS Systems [chapter]

Filipe Moutinho, Luís Gomes
2012 IFIP Advances in Information and Communication Technology  
In both approaches models rely on a synchronous paradigm, which means that all components have to be synchronous within the same clock domain.  ...  This class is used in a model-based development approach to verify GALS systems properties, supporting behavior verification and implementation.  ... 
doi:10.1007/978-3-642-28255-3_16 fatcat:itj6t7ccercm5jr6ejfclxx4hm

Petri Net Based Specification and Verification of Globally-Asynchronous-Locally-Synchronous System [chapter]

Filipe Moutinho, Luís Gomes, Paulo Barbosa, João Paulo Barros, Franklin Ramalho, Jorge Figueiredo, Anikó Costa, André Monteiro
2011 IFIP Advances in Information and Communication Technology  
This paper shows a methodology for Globally-Asynchronous-Locally-Synchronous (GALS) systems specification and verification.  ...  This set of modules is then automatically translated into Maude code through a MDA approach.  ...  Some authors propose a verification approach for GALS systems (e.g.  ... 
doi:10.1007/978-3-642-19170-1_26 fatcat:rt36lfoqqrfqbcfikfe5blz6hi

Guest Editors' Introduction: GALS Design and Validation

Mike Kishinevsky, Sandeep K. Shukla, Kenneth S. Stevens
2007 IEEE Design & Test of Computers  
Would they alleviate the need for a GALS approach to some extent or could they be used in the context of multiple clock domains?  ...  & Given that we have tools for test and verification of synchronous designs, can we design synchronously and then partition the system into synchronous islands, so that the GALS implementation of the design  ... 
doi:10.1109/mdt.2007.166 fatcat:j4y32mb5t5egxkzly4vlirbggq

Verification of GALS Systems by Combining Synchronous Languages and Process Calculi [chapter]

Hubert Garavel, Damien Thivolle
2009 Lecture Notes in Computer Science  
This paper proposes a general approach for modelling and verifying Gals systems using a combination of synchronous languages (for the sequential components) and process calculi (for communication channels  ...  A Gals (Globally Asynchronous Locally Synchronous) system typically consists of a collection of sequential, deterministic components that execute concurrently and communicate using slow or unreliable channels  ...  Acknowledgements We are grateful to Patrick Farail and Pierre Gaufillet (Airbus) for their continuing support and to Claude Helmstetter  ... 
doi:10.1007/978-3-642-02652-2_20 fatcat:tlfbl2pqxjduvo2whtrmhkbyma

Augmenting High-Level Petri Nets to Support GALS Distributed Embedded Systems Specification [chapter]

Filipe Moutinho, Luís Gomes
2013 IFIP Advances in Information and Communication Technology  
This paper proposes to include in high-level Petri nets a set of concepts already introduced for lowlevel Petri nets allowing the specification of GALS systems, namely time domains, test arcs and priorities  ...  Embedded systems components are usually synchronous, which means that DES can be seen as Globally-Asynchronous Locally-Synchronous (GALS) systems.  ...  This work was partially financed by Portuguese Agency "FCT -Fundação para a Ciência e a Tecnologia" in the framework of project PEst-OE/EEI/UI0066/2011.  ... 
doi:10.1007/978-3-642-37291-9_24 fatcat:ljdfpaxxa5bcbmvxt2cm2kqnii

GRL: A Specification Language for Globally Asynchronous Locally Synchronous Systems [chapter]

Fatma Jebali, Frédéric Lang, Radu Mateescu
2014 Lecture Notes in Computer Science  
In this paper, we present a new language, called GRL (GALS Representation Language) designed to model GALS systems in an abstract and versatile manner for the purpose of formal verification.  ...  A GALS (Globally Asynchronous, Locally Synchronous) system consists of several synchronous subsystems that evolve concurrently and interact with each other asynchronously.  ...  Formal modeling and verification is then a crucial part in the design process of such usually safetycritical systems. Many different approaches have been proposed for GALS modeling and verification.  ... 
doi:10.1007/978-3-319-11737-9_15 fatcat:b3lgksjgk5hzbew6fokf3vcopu

Formal modelling and verification of GALS systems using GRL and CADP

Fatma Jebali, Frédéric Lang, Radu Mateescu
2016 Formal Aspects of Computing  
In this paper, we present GRL (GALS Representation Language), a formal language designed to model GALS systems, for the purpose of formal verification of the asynchronous aspects.  ...  A GALS (Globally Asynchronous, Locally Synchronous) system consists of several synchronous components that evolve concurrently and interact with each other asynchronously.  ...  We are grateful toÉric Léo for implementing the GRL2LNT translator and for valuable discussions. We are also grateful to our industrial partners in the Bluesky project for useful feedback  ... 
doi:10.1007/s00165-016-0373-3 fatcat:fnddchkmzzcszojzv2dtnouy7m

The Future of Formal Methods and GALS Design

Kenneth S. Stevens, Daniel Gebhardt, Junbok You, Yang Xu, Vikas Vij, Shomit Das, Krishnaji Desai
2009 Electronical Notes in Theoretical Computer Science  
Modular composition of components through a shared interconnect is now becoming the standard, rather than the exotic.  ...  Asynchronous interconnect fabrics and globally asynchronous locally synchronous (GALS) design has been shown to be potentially advantageous.  ...  An asynchronous GALS network has lower power than the "multi-synchronous" approach for a 4G telephony research chip [29] .  ... 
doi:10.1016/j.entcs.2009.07.032 fatcat:7ae2rt6twfei7iyxmknd7t7poi

Monitoring distributed reactive systems

Yu Bai, Jens Brandt, Klaus Schneider
2012 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)  
Runtime verification has a similar problem since one has to add a monitor to an existing system where typically a synchronous composition is assumed.  ...  Since the modules of these systems can derive their own local clocks from their inputs, they can be implemented as asynchronous components without inefficient synchronizations.  ...  For the sake of simplicity, first assume that we want to monitor a single (endochronous) component of a GALS system.  ... 
doi:10.1109/hldvt.2012.6418247 dblp:conf/hldvt/BaiBS12 fatcat:4m4aoawmlra23av4motss5cage

Enhanced GALS Techniques for Datapath Applications [chapter]

Eckhard Grass, Frank Winkler, Miloš Krstić, Alexandra Julius, Christian Stahl, Maxim Piz
2005 Lecture Notes in Computer Science  
Secondly, to reduce supply noise, a novel approach applying individual clock jitter for GALS blocks is proposed.  ...  A simulation using the jitter technique shows that for a typical GALS system, the power spectrum of the supply current can be reduced by about 15 dB.  ...  Secondly, we propose the introduction of jitter for de-synchronizing the operation of different GALS blocks. This will reduce EMI and hence facilitate the integration of complex mixed-signal chips.  ... 
doi:10.1007/11556930_59 fatcat:saf6bc6izbagvamzszlfumzu7q

Asynchronous Design—Part 1: Overview and Recent Advances

Steven M. Nowick, Montek Singh
2015 IEEE design & test  
Acknowledgment The authors appreciate the funding support of the National Science Foundation under Grants CCF-1219013, CCF-0964606 and OCI-1127361.  ...  In its original and widely-used sense, 1,3,4 a GALS system includes a fully-asynchronous interconnection network, including handshaking channels, to integrate synchronous components.  ...  In its original and widely-used sense, 1,3,4 a GALS system includes a fully-asynchronous interconnection network, includ-s ing handshaking channels, to integrate synchronous components.  ... 
doi:10.1109/mdat.2015.2413759 fatcat:g5qkrrrdujdkld6fsx3fhyrem4

Asynchronous on-chip networks

M. Amde, T. Felicijan, A. Efthymiou, D. Edwards, L. Lavagno
2005 IEE Proceedings - Computers and digital Techniques  
A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms.  ...  Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs.  ...  The synchronous model takes advantage of verification tools available for the synchronous languages.  ... 
doi:10.1049/ip-cdt:20045093 fatcat:jedytsssjfcmjoyrajrn47ue6e

Verifying the Safety of a Flight-Critical System [article]

Guillaume Brat, David Bushnell, Misty Davies, Dimitra Giannakopoulou, Falk Howar, Temesghen Kahsai
2015 arXiv   pre-print
; processing models for their use by formal verification tools; applying compositional techniques at the architectural and component level to scale verification.  ...  Performed in the context of a major NASA milestone, this study of formal verification in practice is one of the most challenging that our group has performed, and it took several person months to complete  ...  Compositional verification constructs a verification argument for a complex system by composing simpler verification results at the level of the system components.  ... 
arXiv:1502.02605v1 fatcat:ma6s7wwrkvcxznmkbbx6tnzlpm

Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages

Jian Liu, Steven M. Nowick, Mingoo Seok
2013 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems  
forming globally-asynchronous locally-synchronous (GALS) systems, where the asynchronous network provides a scalable and reliable integration medium.  ...  A post-layout evaluation of the new switch design, in comparison with the synchronous xpipesLite implementation, demonstrated: a reduction in overall power of 85%/73% (vs. synchronous without/with clock  ...  The goal is a GALS network, that can integrate multiple synchronous cores and caches operating at unrelated clock rates.  ... 
doi:10.1109/async.2013.29 dblp:conf/async/LiuNS13 fatcat:pgi4on5mbffj3fylrygmhghspy
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