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Convolution, deconvolution, and mean field annealing suitable for analog VLSI

G.L. Bilbro, L.C. Hall, M. Clements, Wentai Liu
1999 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
We formulate several standard digital image processing operations as circuits suitable for implementation in real-time analog VLSI, including nonlinear piecewise-constant image restoration using mean field  ...  We report test results from an imaging chip that performs user-controlled convolution of the image.  ...  real-time applications, even when implemented on a 64-node hypercube parallel architecture [4] .  ... 
doi:10.1109/82.752912 fatcat:j7sofauofbayvju6xjmrrc5ws4

Wavelet transform architectures: A system level review [chapter]

M. Ferretti, D. Rizzo
1997 Lecture Notes in Computer Science  
Indeed, common VLSI cost functions (such as AT ~-) are insufficient to evaluate architectures for compression.  ...  In this paper we review the architectures designed for wavelet transi:brms, with the purpose to highlight their suitability for inclusion in codec systems.  ...  The architecture can reuse the hardware for the convolution kernel, albeit with a rather different I/O and timing structure.  ... 
doi:10.1007/3-540-63508-4_108 fatcat:ql2uhz3f2rdyjk2jkxd5jh7sou

A systolic processor for signal processing

G. A. Frank, E. M. Greenawalt, A. V. Kulkarni
1982 Proceedings of the June 7-10, 1982, national computer conference on - AFIPS '82  
These new systolic architectures allow the real-time design of adaptive filters.  ...  ESL is also pursuing new types of systolic architectures, including the VLSI implementation of systolic cells for solving systems of linear equations.  ...  The processor is used more than 80% of the time for large I-D convolutions. The use drops off for problems with small-sized kernels as the nonoverlapped I/O time becomes significant.  ... 
doi:10.1145/1500774.1500801 dblp:conf/afips/FrankGK82 fatcat:dlcqjockobhcdoyg4vwkeb7puu

Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor

Alireza Nilchi, Joseph Aziz, Roman Genov
2009 IEEE Journal of Solid-State Circuits  
The CMOS image sensor computes two-dimensional convolution of video frames with a programmable digital kernel of up to 8 8 pixels in parallel directly on the focal plane.  ...  Three operations, a temporal difference, a multiplication and an accumulation are performed for each pixel readout. A dual-memory pixel stores two video frames.  ...  It computes block-matrix and convolutional transforms as well as frame difference on the focal plane for real-time spatio-temporal video processing.  ... 
doi:10.1109/jssc.2009.2016693 fatcat:2cc7fhi4vvhrfju2caxw5ekiva

High-speed architectures for digital image processing

A. Venetsanopoulos, K. Ty, A. Loui
1987 IEEE Transactions on Circuits and Systems  
A modular VLSI architecture based on the decomposition of the kernel matrix of a two-dimensional (2-D) transfer function is also presented.  ...  Absiract-This paper introduces the problem of and presents some state-of-the-art approaches for high-speed digital image processing.  ...  A number of new architectures capable of achieving real-time or near real-time image processing will be presented in this paper.  ... 
doi:10.1109/tcs.1987.1086238 fatcat:cf22sud3ofazdko6imkipeed3a

Kerneltron: support vector "machine" in silicon

R. Genov, G. Cauwenberghs
2003 IEEE Transactions on Neural Networks  
The mixed-signal very large-scale integration (VLSI) processor is dedicated to the most intensive of SVM operations: evaluating a kernel over large numbers of vectors in high dimensions.  ...  computational power required of the trained classifier running real-time.  ...  For large scale problems as the ones of interest here, the dimensions of the matrix are excessive for real-time implementation even on a high-end processor.  ... 
doi:10.1109/tnn.2003.816345 pmid:18244588 fatcat:2673tdaqivcnpaqdn27xbldhh4

Kerneltron: Support Vector 'Machine' in Silicon [chapter]

Roman Genov, Gert Cauwenberghs
2002 Lecture Notes in Computer Science  
The mixed-signal very large-scale integration (VLSI) processor is dedicated to the most intensive of SVM operations: evaluating a kernel over large numbers of vectors in high dimensions.  ...  computational power required of the trained classifier running real-time.  ...  For large scale problems as the ones of interest here, the dimensions of the matrix are excessive for real-time implementation even on a high-end processor.  ... 
doi:10.1007/3-540-45665-1_10 fatcat:onimogasmjdmzglhowytcxoslu

Focal-plane analog VLSI cellular implementation of the boundary contour system

G. Canwenberghs, J. Waskiewicz
1999 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
We present an analog very large scale integration (VLSI) cellular architecture implementing a version of the boundary contour system (BCS) for real-time focal-plane image processing.  ...  Experimental results from a fabricated 12 2 10 pixel prototype in a 1.2-m CMOS process are included, demonstrating the robustness of the implemented BCS model in selecting image contours in a cluttered  ...  The analog VLSI implementation of BCS reported here is a first step toward this goal, with the additional objectives of real-time low-power operation, as required for demanding target recognition applications  ... 
doi:10.1109/81.747215 fatcat:cga3654ivzeldjcz47rrpu43g4

Linear Interpolation Algorithms and their Architectures for Image Scaling – A Survey

C John Moses, D Selvathi, G Shaya Edal Queen
2017 DJ Journal of Advances in Electronics and Communication Engineering  
These algorithms are implemented for different Very Large Scale Integrated Circuit (VLSI) based implementations such as Field Programmable Gate Array (FPGA) and Complementary Metal Oxide Semiconductor  ...  It also provides a better image quality. It requires only two pixels to calculate the interpolated pixel value.  ...  Piecewise Linear Convolution Interpolation with Third- order Approximation for Real-time Image Processing, IEEE International Conference on Systems Man and Cybernetics (SMC), Turkey, 2010, pp. 3632  ... 
doi:10.18831/djece.org/2018011001 fatcat:j7f3c6zfqjfvppowl7b2yf37cq

A real-time volume rendering architecture using an adaptive resampling scheme for parallel and perspective projections

Masato Ogata, TakaHide Ohkami, Hugh C. Lauer, Hanspeter Pfister
1998 Proceedings of the 1998 IEEE symposium on Volume visualization - VVS '98  
This paper describes an object-order real-time volume rendering architecture using an adaptive resampling scheme to perform resampling operations in a unified parallel-pipeline manner for both parallel  ...  The proposed convolution block is organized using a systolic array structure, which works well with a distributed skewed memory for conflict-free accesses of voxels.  ...  Technology Center America for their support.  ... 
doi:10.1145/288126.288146 dblp:conf/vvs/OgataOLP98 fatcat:iersgylgbbayfpxqpdiojyje2a

Image sharpness and beam focus VLSI sensors for adaptive optics

M. Cohen, G. Cauwenberghs, M.A. Vorontsov
2002 IEEE Sensors Journal  
We present two analog very-large-scale-integration (VLSI) image-plane sensors that supply real-time metrics of image and beam quality, for applications in imaging and line-of-sight laser communication.  ...  Index Terms-Adaptive optics, analog very large scale integration (VLSI), focal-plane image processing, image sensors, optical communication.  ...  Banta of the Intelligent Optics Laboratory at the Army Research Laboratories for their assistance with optical experiments and data collection. Chips were fabricated through the MOSIS foundry.  ... 
doi:10.1109/jsen.2002.807298 fatcat:tmdtrrlxurc63er2bb3wtnabtu

On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing

R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jimenez, C. Serrano-Gotarredona, J.A. Perez-Carrasco, B. Linares-Barranco, A. Linares-Barranco, G. Jimenez-Moreno, A. Civit-Ballcels
2008 IEEE Transactions on Neural Networks  
In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented.  ...  As a first test prototype, a pixel array of 16 16 has been implemented with programmable kernel size of up to 16 16.  ...  A clever DSP architecture specialized for large kernel convolutions was presented in 1999 by Wall et al. [12] .  ... 
doi:10.1109/tnn.2008.2000163 fatcat:csfzlmw6ibcdpbceorrdixydz4

A High Speed Architecture for Lifting-based 2-D Cohen-Daubechies-Feauveau (5,3) Discrete Wavelet Transform used in JPEG2000

Mohammad Rafi Lone, Najeed- Ud-Din
2017 International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems  
For real-time applications, efficient VLSI implementation of DWT is desired. In this paper, DWT architecture based on retiming for pipelining and unfolding is presented.  ...  This can be utilized for real-time video processing applications even for high resolution videos.  ...  Such an implementation requires both, a large number of computation and a large storage which are undesirable for any high speed or low power application.  ... 
doi:10.11601/ijates.v6i1.202 fatcat:no3nttfbavg2bntcmcmhjvksoq

Two fast architectures for the direct 2-D discrete wavelet transform

F. Marino
2001 IEEE Transactions on Signal Processing  
2 In this paper, we will consider nonseparable 2-D filter bases working with separable sampling patterns.  ...  Therefore, even though the separable approach allows "recycling" of devices designed for 1-D applications, when a device has to be explicitly designed for 2-D application, or when real-time performance  ...  Publisher Item Identifier S 1053-587X(01)03892-2. images are considerable) and represents an additional latency that strongly reduces the possibility of real time processing.  ... 
doi:10.1109/78.923307 fatcat:t54vn33vxvexvioiru7ckwvaxu

Novel Parallel Approach for SIFT Algorithm Implementation

Tran Su Le, Jong-Soo Lee
2013 Journal of information and communication convergence engineering  
perform real-time image and video compression.  ...  This paper proposes a novel parallel approach for SIFT algorithm implementation using a block filtering technique in a Gaussian convolution process on the SIMD Pixel Processor.  ...  (1) and (2) , * denotes the convolution operator, G(x, y, σ) represents a variable-scale Gaussian kernel, I(x, y) refers to the input image, and k is used for increasing or decreasing the scale.  ... 
doi:10.6109/jicce.2013.11.4.298 fatcat:o2dvbkyxxjdr3pcnmfwx3dbade
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