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Analog VLSI neural network with digital perturbative learning

V.F. Koosh, R.M. Goodman
2002 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
The first uses analog synapses and neurons with a digital serial weight bus. The chip is trained in loop with the computer performing control and weight updates.  ...  Index Terms-Analog very large scale integration (VLSI), chip-in-loop training algorithm, learning, neural chips, neural network, neuromorphic, perturbation techniques, VLSI feed-forward neural network.  ...  Since one side of the differential current inputs may have a larger share of the common mode current, it is important to distribute this common mode to keep both differential currents within a reasonable  ... 
doi:10.1109/tcsii.2002.802282 fatcat:my2dquugtvaszmvh37zkukpn6i

Focal-Plane and Multiple Chip VLSI Approaches to CNNs [chapter]

Mancia Anguita, Francisco J. Pelayo, Eduardo Ros, David Palomar, Alberto Prieto
1998 Cellular Neural Networks and Analog VLSI  
, a compact fixed-template CNN based on unipolar current-mode signals, and basic CMOS circuits to implement an extended CNN model using spikes.  ...  Most of the experimental results reported to date refer to the processing of optical information, although in practice, only a few CNN chips integrate on-chip photo-sensors (focal-plane solutions [7, 11  ...  Compact CMOS Unipolar Current-Mode CNN Implementation The current-mode implementations of CNNs usually work with both positive and negative currents.  ... 
doi:10.1007/978-1-4757-4730-0_4 fatcat:b5gndatzizguhhb3wtnwilf7q4

Programmable Spike-Timing-Dependent Plasticity Learning Circuits in Neuromorphic VLSI Architectures

Mostafa Rahimi Azghadi, Saber Moradi, Daniel B. Fasnacht, Mehmet Sirin Ozdas, Giacomo Indiveri
2015 ACM Journal on Emerging Technologies in Computing Systems  
Here we present a neuromorphic multi-neuron VLSI device with on-chip programmable event-based hybrid analog/digital circuits; the event-based nature of the input/output signals allows the use of address-event  ...  it, and we demonstrate how, after training, the VLSI device can perform as a standalone component (i.e., without requiring a computer), binary classification of correlated patterns.  ...  CONCLUSIONS We presented a hybrid SW-HW neuromorphic system that utilizes a previously developed programmable neuromorphic VLSI device (IFMEM chip) that comprises silicon neurons and event-driven synapses  ... 
doi:10.1145/2658998 fatcat:2qi46cgx4nbxtpyqqyngzz5d64

An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory

Saber Moradi, Giacomo Indiveri
2014 IEEE Transactions on Biomedical Circuits and Systems  
These currents are further integrated by current-mode integrator synapses to produce biophysically realistic temporal dynamics.  ...  The fabricated chip comprises a total of 32 32 SRAM cells, 4 32 synapse circuits and 32 1 silicon neurons.  ...  ACKNOWLEDGMENT The authors would like to thank A.  ... 
doi:10.1109/tbcas.2013.2255873 pmid:24681923 fatcat:gckgyknizfapjcshxnn3yva3xm

Spike-based learning in VLSI networks of integrate-and-fire neurons

Giacomo Indiveri, Stefano Fusi
2007 2007 IEEE International Symposium on Circuits and Systems  
We describe the architecture of a spike-based learning neural network, the analog circuits that implement the synaptic learning mechanism, and present results from a prototype VLSI chip comprising a full  ...  network of integrate-and-fire neurons and plastic synapses.  ...  ACKNOWLEDGMENT The design of the VLSI chip and the experimental measurements were done together with Srinjoy Mitra.  ... 
doi:10.1109/iscas.2007.378290 dblp:conf/iscas/IndiveriF07 fatcat:4wenzwug7zbtjoaboszz4e6mom

A current-mode spiking neural classifier with lumped dendritic nonlinearity

Amitava Banerjee, Sougata Kar, Subhrajit Roy, Aritra Bhaduri, Arindam Basu
2015 2015 IEEE International Symposium on Circuits and Systems (ISCAS)  
We present the current mode implementation of a spiking neural classifier with lumped square law dendritic nonlinearity.  ...  The chip fabricated in 0.35µm CMOS has 8 dendrites per cell and uses two opposing cells per class to cancel common mode inputs.  ...  The DPI synapse, square block and the neuron combined together forms a basic unit of the fabricated chip governed by equation (8) .  ... 
doi:10.1109/iscas.2015.7168733 dblp:conf/iscas/BanerjeeKRBB15 fatcat:ltvngxttifbcji5ktt5kjbyd6m

An Energy-efficient Time-domain Analog VLSI Neural Network Processor Based on a Pulse-width Modulation Approach [article]

Masatoshi Yamaguchi, Goki Iwamoto, Hakaru Tamukoh, Takashi Morie
2019 arXiv   pre-print
We designed a CMOS VLSI chip to verify weighted-sum operation based on the proposed model with binary weights, which realizes the BinaryConnect model.  ...  The chip was designed and fabricated using a 250-nm fabrication technology.  ...  The circuit design was supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc., Mentor Graphics, Inc., and Synopsys, Inc.  ... 
arXiv:1902.07707v1 fatcat:ekto5squdnfhzdksn6bdif7eyq

Exploiting device mismatch in neuromorphic VLSI systems to implement axonal delays

Sadique Sheik, Elisabetta Chicca, Giacomo Indiveri
2012 The 2012 International Joint Conference on Neural Networks (IJCNN)  
We describe the chip architecture and the analog circuits used to implement the neurons and synapses.  ...  Each neuron integrates input currents from a row of multiple analog synaptic circuit.  ...  refresh circuit (see transconductance amplifier in Fig. 4a ), and a current-mode DPI circuit (not shown).  ... 
doi:10.1109/ijcnn.2012.6252636 dblp:conf/ijcnn/SheikCI12 fatcat:zuzfcpyzmzdrzizwirshn4xkue

Context dependent amplification of both rate and event-correlation in a VLSI network of spiking neurons [chapter]

2007 Advances in Neural Information Processing Systems 19  
We propose a VLSI implementation of a spiking cooperative competitive network and show how it can perform context dependent computation both in the mean firing rate domain and in spike timing correlation  ...  Cooperative competitive networks are believed to play a central role in cortical processing and have been shown to exhibit a wide set of useful computational properties.  ...  We are currently in the process of designing an equivalent architecture one a new chip using an AMS 0.35µm technology, with 256 neurons and 8192 synapses.  ... 
doi:10.7551/mitpress/7503.003.0037 fatcat:625kpmxkarcnpkdmcqtrmbkpdi

A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning

Xinyu Wu, Vishal Saxena, Kehan Zhu, Sakkarapani Balagopal
2015 IEEE Transactions on Circuits and Systems - II - Express Briefs  
This work presents a novel leaky integrate-and-fire neuron design which implements the dual-mode operation of current integration and synaptic drive, with a single opamp and enables in-situ learning with  ...  To realize such a brain-inspired computing chip, a compact CMOS spiking neuron that performs in-situ learning and computing while driving a large number of resistive synapses is desired.  ...  Fig. 3 . 3 Dual-mode operation. (A) Integration mode: opamp is configred as a leaky integrator to sum the currents injected into the neuron.  ... 
doi:10.1109/tcsii.2015.2456372 fatcat:cxpn3d3btfhv7lr7txmsdtkdda

Computation in Neuromorphic Analog VLSI Systems [chapter]

Giacomo Indiveri
2002 Perspectives in Neural Computing  
We present the main principles used by the neuromorphic engineering community and describe, as case example, a neuromorphic VLSI system for modeling selective visual attention.  ...  These VLSI systems, rather than implementing abstract neural networks only remotely related to biological systems, in large part, directly exploit the physics of silicon (and of CMOS VLSI technology) to  ...  To the extent that the physics of the transistors matches well the computation to be performed, and digital communication between chips is small, the analog VLSI circuits use less power and silicon area  ... 
doi:10.1007/978-1-4471-0219-9_1 dblp:conf/wirn/Indiveri01 fatcat:b3rfkeuhwbeujirov45u5t243i

A Model of Stimulus-Specific Adaptation in Neuromorphic Analog VLSI

Robert Mill, Sadique Sheik, Giacomo Indiveri, Susan L. Denham
2011 IEEE Transactions on Biomedical Circuits and Systems  
In this paper we present a model of SSA based on synaptic depression and describe its implementation in neuromorphic analog very-large-scale integration (VLSI).  ...  when a different stimulus is presented.  ...  ACKNOWLEDGMENT The 2D multi-neuron chip was designed and developed by Elisabetta Chicca. The authors would like to thank M.  ... 
doi:10.1109/tbcas.2011.2163155 pmid:23852174 fatcat:mk355cpycvekxd3gpzoalzmufy

A VLSI network of spiking neurons with an asynchronous static random access memory

Saber Moradi, Giacomo Indiveri
2011 2011 IEEE Biomedical Circuits and Systems Conference (BioCAS)  
To store synaptic weight values, we designed a novel asynchronous SRAM block, integrated it on chip and connected it to the dynamic synapse circuits, via a fast current-mode DAC.  ...  In this paper we present an asynchronous VLSI neuromorphic architecture comprising an array of integrate and fire neurons and dynamic synapse circuits with programmable weights.  ...  The synaptic currents were measured by reading a local copy of the relevant I syn current off-chip, and by using an off-chip current to voltage converter.  ... 
doi:10.1109/biocas.2011.6107781 fatcat:dd4rm527d5dtvdncn4uldapp6u

Function approximation with uncertainty propagation in a VLSI spiking neural network

Dane Corneil, Daniel Sonnleithner, Emre Neftci, Elisabetta Chicca, Matthew Cook, Giacomo Indiveri, Rodney Douglas
2012 The 2012 International Joint Conference on Neural Networks (IJCNN)  
Here, we demonstrate a distributed spiking neural network architecture comprising multiple neuromorphic VLSI chips able to reproduce these types of cue combination and integration operations.  ...  This is achieved by encoding cues as population activities of input nodes in a network of recurrently coupled VLSI Integrate-and-Fire (I&F) neurons.  ...  a current-mode Winner-Take-All (WTA) network.  ... 
doi:10.1109/ijcnn.2012.6252780 dblp:conf/ijcnn/CorneilSNCCID12 fatcat:vr5mkd6fdzcopfsey4hovm5tve

Quantification of a Spike-Based Winner-Take-All VLSI Network

Matthias Oster, Yingxue Wang, Rodney Douglas, Shih-Chii Liu
2008 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Abstract We describe a formalism for quantifying the performance of spike-based winner-take-all (WTA) VLSI chips.  ...  Abstract-We describe a formalism for quantifying the performance of spike-based winner-take-all (WTA) VLSI chips.  ...  Programmable Local Synaptic Weights The DAC block consists of two global current-mode 5-bit DAC. These converters are used to set the weights of individual synapses.  ... 
doi:10.1109/tcsi.2008.923430 fatcat:fy5puc56nveqxi3sqdxobrkexu
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