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A real-time wavelet vector quantization algorithm and its VLSI architecture

Seung-Kwon Paek, Lee-Sup Kim
2000 IEEE transactions on circuits and systems for video technology (Print)  
PE's are for Euclidean distance calculation and a PE is for parallel distance comparison.  ...  The proposed WVQ VLSI architecture has only one VQ module to execute in real-time the proposed zerotree WVQ algorithm by utilizing the vacant cycles for zero-vector trees which are not transmitted.  ...  Fig. 5 . 5 VQ VLSI architecture for MSVQ and CVQ. Fig. 6 .Fig. 7 .Fig. 8 . 678 Cost-effective VQ VLSI architecture for MSVQ and CVQ. PE VLSI architecture. (a) IPU.  ... 
doi:10.1109/76.836293 fatcat:pbzs7qyg2ng3hpldeeg4prv2ja

Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network

Xu BAI, Michitaka KAMEYAMA
2014 IEICE transactions on information and systems  
A global pipelined tree network is utilized to realize high-performance long-distance bit-parallel data transfer.  ...  using only the X-net network. key words: multiple-valued reconfigurable VLSI, fine-grain reconfigurable VLSI, global tree local X-net network, logic-in-memory architecture  ...  Acknowledgments This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with STARC, e-Shuttle, Inc., Fujitus Ltd., Cadence Design Systems, Inc. and Synopsys  ... 
doi:10.1587/transinf.2013lop0006 fatcat:3kdodnjltjdopkfkmffnrcjd3a

Probabilistic Spherical Detection and VLSI Implementation for Multiple-Antenna Systems

C.S. Park, K.K. Parhi, Sin-Chong Park
2009 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
An efficient VLSI architecture is proposed for implementation of the P-SD algorithm, and the results of the synthesized architecture are presented.  ...  By confining the tree search into candidates which can be selected in an adaptive manner, a large number of promising candidates can be evaluated before termination.  ...  ACKNOWLEDGMENT The authors would like to thank J. Lee and Y. Zhang for their valuable comments. They would also like to thank the anonymous reviewers for their comments and suggestions.  ... 
doi:10.1109/tcsi.2008.2002544 fatcat:jmiai3vcqjddzlvk2jxhbunjvq

A High Performance VLSI Architecture for MIMO Detection in Future WLAN Receivers

Ramin Shariat-Yazdi, Tadeusz Kwasniewski
2007 2007 Canadian Conference on Electrical and Computer Engineering  
The proposed architecture is implemented in 0.18 µm technology for a 4x4 QPSK MIMO system and was able to achieve a decoding throughput of 60 Mbps.  ...  In this paper a new VLSI architecture for implementation of sphere decoding algorithm is proposed. The proposed architecture is fully parallel and designed based on the stack operation.  ...  CONCLUSION In this paper a new VLSI architecture for sphere decoding algorithm has been proposed.  ... 
doi:10.1109/ccece.2007.368 fatcat:y76vnnilmjay7b4n7pavmyrv5i

Variant X-Tree Clock Distribution Network and Its Performance Evaluations

X. ZHANG, X. JIANG, S. HORIGUCHI
2007 IEICE transactions on electronics  
In this paper, we propose a new clock distribution network (CDN), namely Variant X-Tree, based on the idea of X-Architecture proposed recently for efficient wiring within VLSI chips.  ...  We also propose a closed-form statistical models for evaluating the skew and delay of the Variant X-Tree CDN.  ...  Therefore we consider that it is enough for most of CDNs and suitable to the semi-global or global clock distribution on a VLSI chip. † H-Tree CDN can be considered as a Variant X-Tree CDN where the distance  ... 
doi:10.1093/ietele/e90-c.10.1909 fatcat:zrq4ghqbhjghpj3zfrqlfl6ivm

A segmented parallel-prefix VLSI circuit with small delays for small segments

Bradley C. Kuszmaul
2005 Proceedings of the 17th annual ACM symposium on Parallelism in algorithms and architectures - SPAA'05  
I present a VLSI circuit for segmented parallel prefix with gate delay O(log S) and wire delay O( √ S) for segment size S, and total area O(N).  ...  Thus, for example, for the problem of adding random numbers, in most cases, the addition would complete with only O(log log N) gate delay and O( √ log N) wire delay.  ...  SUMMARY One of the limitations to increasing clock speed for microprocessors is the time required for a VLSI circuit to perform an addition of two integers [1] .  ... 
doi:10.1145/1073970.1074002 dblp:conf/spaa/Kuszmaul05 fatcat:yslmxzetjbgw3jhxxkzrp4labi

Visual Vocabulary Processor Based on Binary Tree Architecture for Real-Time Object Recognition in Full-HD Resolution

Tse-Wei Chen, Yu-Chi Su, Keng-Yen Huang, Yi-Min Tsai, Shao-Yi Chien, Liang-Gee Chen
2012 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The VVP can transform hundreds of 128-D SIFT vectors into a 64-D histogram for object matching by using the binary-tree-based architecture, and 16 calculators for the computations of the Euclidean distances  ...  with the nonbinary-tree-based architecture.  ...  ACKNOWLEDGMENT The authors would like to thank TSMC University Shuttle Program and Jefferson Hsieh for process support.  ... 
doi:10.1109/tvlsi.2011.2170203 fatcat:xqz2ps2g6ndu3gytm5mlrb3rym

On the VLSI Implementation of low complexity K-best MIMO decoders

Sudip Mondal, Khaled N Salama, Ahmed Eltawil
2008 2008 International Conference on Microelectronics  
The VLSI Implementation of Maximum Likelihood (ML) detection for higher order Multiple Input Multiple Output (MIMO) systems continues to be a major challenge.  ...  This paper presents a modified, low complexity K-best detector for a 4 × 4, 64 QAM MIMO system , which uses a modified path extension algorithm to bring down the computational complexity by more than 50%  ...  We would like to thank the Center for Automation Technologies and Systems (CATS), who has supported this work in part through a block grant from the New York State Foundation for Science, Technology and  ... 
doi:10.1109/icm.2008.5393766 fatcat:2xmhe6osx5hmhovjxwrd72pu4m

Advanced receiver algorithms for MIMO wireless communications

A. Burg, M. Borgmanr, M. Wenk, C. Studer, H. Bolcskei
2006 Proceedings of the Design Automation & Test in Europe Conference  
In particular, algorithms and VLSI architectures for sphere decoding (SD) and K-best detection are considered, and the corresponding trade-offs between uncoded error-rate performance, silicon area, and  ...  We describe the VLSI implementation of MIMO detectors that exhibit close-to optimum error-rate performance, but still achieve high throughput at low silicon area.  ...  VLSI Architectures for Sphere Decoding The SD algorithm can be implemented efficiently using a one-node-per-cycle VLSI architecture [6] , for which the block diagram is shown in Fig. 3 (a).  ... 
doi:10.1109/date.2006.243974 dblp:conf/date/BurgBWSB06 fatcat:se6ehk3535fijg2vzyl7s5ritm

A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding

Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2010 IEEE Transactions on Circuits and Systems - II - Express Briefs  
In this paper, we introduce the - to our best knowledge - first VLSI architecture for SISO SD applying a single tree-search approach.  ...  Compared with a soft-output-only base architecture similar to the one proposed by Studer et al. in IEEE J-SAC 2008, the architectural modifications for soft input still allow a one-node-per-cycle execution  ...  A VLSI ARCHITECTURE FOR STS SOFT-INPUT SPHERE DECODING In this section, a VLSI architecture for SISO STS SD is introduced.  ... 
doi:10.1109/tcsii.2010.2056014 fatcat:fceenb3fmvd7rdkwmvutihk2uy

Fault Tolerance of Programmable Devices [chapter]

Minoru Watanabe
2010 Parallel and Distributed Computing  
To implement such large-scale parallel computation onto a VLSI chip, the demand for a largedie VLSI chip is increasing daily.  ...  As a result, the architecture can realize extremely high-gate-count VLSIs and can support large-scale parallel computation.  ...  Parallel and Distributed Computing The 14 chapters presented in this book cover a wide variety of representative works ranging from hardware design to application development.  ... 
doi:10.5772/9451 fatcat:guq57wdpvffltgq7v4yjg4a7la

A Study on Applying Parallelism for Construction of Steiner Tree Algorithms in VLSI Design

Shyamala G., Latha N.
2016 International Journal of Computer Applications  
Here, we present a survey of the parallel methods for solving the stiener tree problem specifically for VLSI design General Terms Multicore Architecture, Parallel computing, VLSI  ...  We present a survey of the different approaches that can be parallelized and also the parallel algorithms available today with special concern to Rectilinear steiner tree for VLSI Design and their appropriateness  ...  One of the types of Steiner tree problem is the Rectilinear Steiner tree that considers rectilinear or Manhattan distance between a pair of points.  ... 
doi:10.5120/ijca2016911006 fatcat:i7y4vwl2w5fetigheio2tl4l3q

An Efficient Rectilinear and Octilinear Steiner Minimal Tree Algorithm for Multidimensional Environments

Ming Che Lee, Gene Eu Jan, Chung Chin Luo
2020 IEEE Access  
The major contributions of this paper are (1) our work is the first report for the octilinear SMTs in the multidimensional environments, (2) we provide an optimal point-to-point routing without any refinement  ...  This paper proposes an obstacle-avoiding 4/8/10/26-directional heuristic algorithm for this problem based on the Areibi's concept, Higher Geometry Maze Routing, and Sollin's minimal spanning tree algorithm  ...  Lemma 3: The length of any Steiner minimal trees in octilinear architecture computed by this algorithm will be equal to or small than the length of the minimal spanning tree for the same set of nodes in  ... 
doi:10.1109/access.2020.2977825 fatcat:il2zkodgznephfq65d2wxcbgqi

Reduced-Complexity k-best Decoder for LTE Standard

Shirly Edward A., Malarvizhi S.
2015 International Journal of Multimedia and Ubiquitous Engineering  
Therefore, the maximum achievable clock frequency for PED unit is found to  ...  This paper presents a VLSI implementation of reduced -complexity and reconfigurable MIMO(Multiple-Input Multiple-Output) signal detector targeting 3GPP-LTE standard.  ...  In [8] , Wong proposed a pipelined VLSI architecture for the K-best algorithm.  ... 
doi:10.14257/ijmue.2015.10.3.36 fatcat:n4fonpqutbesrkdglobnphh5he

Supporting tasks with adaptive groups in data parallel programming

John O'Donnell
2005 International Journal of Computational Science and Engineering (IJCSE)  
A set of communication operations is defined which allows a form of task parallelism to be achieved in a data parallel architecture.  ...  The groups may be subdivided and recombined at any time, allowing the task structure to adapt to the needs of the data.  ...  ACKNWLEDGEMENT I would like to thank the anonymous referees and the editors for several helpful suggestions.  ... 
doi:10.1504/ijcse.2005.009694 fatcat:kgns6v37cjhbfnhotm4tttrq7a
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