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Memory Efficient LUT Based Address Generator for OFDM-WiMAX De-Interleaver

Bijoy Kumar Upadhyaya, Pranab Kumar Goswami, Salil Kumar Sanyal
2014 International Journal of Electronics and Electrical Engineering  
In this paper, a memory efficient Look-up Table ( LUT) based address generator for the de-interleaver used in OFDM-WiMAXtransreceiver is proposed.  ...  The relationships between various address LUTs implementing different interleaver / de-interleaver depths within a modulation scheme have been exploited to model the proposed address generator.  ...  This relationship between the address LUTs is used to propose a novel memory efficient LUT based address generator for WiMAX de-interleaver.  ... 
doi:10.12720/ijeee.2.1.31-35 fatcat:6sw47cfm75dkpbv4gzsfl75s7q

The CMS Modular Track Finder boards, MTF6 and MTF7

D Acosta, G Brown, A Carnes, M Carver, D Curry, G P Di Giovanni, I Furic, A Kropivnitskaya, A Madorsky, M Matveev, P Padley, D Rank (+3 others)
2013 Journal of Instrumentation  
Also presented are plans for the pre-production prototype based on the Virtex-7 FPGA family, MTF7.  ...  The Core Logic module houses the large FPGA that contains the processing logic and multi-gigabit serial links for data exchange.  ...  Gorski (University of Wisconsin, Madison) for providing firmware, software, and support for the MMC design.  ... 
doi:10.1088/1748-0221/8/12/c12034 fatcat:wvvd4bdfpzddbbai2etkjq2e2u

Design and Implementation of Modular FPGA-Based PID Controllers

Yuen Fong Chan, M. Moallem, Wei Wang
2007 IEEE transactions on industrial electronics (1982. Print)  
These reusable modules can be ported into Matlab/Simulink as Simulink blocks for hardware/software cosimulation or integrated into a larger design in the Matlab/Simulink environment to allow for rapid  ...  The complete digital control system is built using commercial FPGAs to demonstrate the efficiency. The design uses a modular approach, so that some modules can be reused in other applications.  ...  ACKNOWLEDGMENT The FPGA development environment was donated by Canadian Microelectronics Corporation, Kingston, ON, Canada.  ... 
doi:10.1109/tie.2007.898283 fatcat:pxv5o72uwzeutetltgomojysy4

On the Design of a Reconfigurable Radio Processor Using FPGA

Amiya Karmakar, Amrita Saha, Amitabha Sinha
2014 Journal of clean energy technologies  
FPGA based implementation of the proposed architecture reveals that the number of LUTs is reduced by 11.11% compared to the sum of individual LUTs used for each of the modulation scheme.  ...  Keeping these issues in view, this paper proposes a flexible architecture that combines five different modulation schemes.  ...  control unit to generate the control signals for a given scheme.  ... 
doi:10.7763/ijcte.2014.v6.841 fatcat:tfrnqoutpng73ji6o3s7ymamwy

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design

Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA
2013 IEICE transactions on information and systems  
This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design.  ...  The FPGA based on the proposed architecture is implemented in a 65 nm process. Its evaluation results show that the proposed FPGA can implement handshake components efficiently.  ...  Acknowledgment This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with STARC, e-Shuttle, Inc., Fujitsu Ltd., Cadence Design Systems Inc. and Synopsys  ... 
doi:10.1587/transinf.e96.d.1632 fatcat:k7i2owfrv5eifla36qlyonvwe4

CORDIC based Universal Modulator

Lt Parichay Kalra, Naresh Vemishetty, B Venkatramani
2014 2014 Recent Advances in Engineering and Computational Sciences (RAECS)  
In the literature, different architectures have been proposed for FPGA implementation of Universal Modulator. The Look up table (LUT) technique is one way of realizing universal modulator.  ...  In this paper, a pipelined CORDIC using 2 stages of Multiplexer is proposed for efficient realization of universal modulator.  ...  The objective of this paper is to extend the scheme proposed in [3] for the implementation of CORDIC based universal modulator on Spartan 3E FPGA.  ... 
doi:10.1109/raecs.2014.6799562 fatcat:2ilstbcqnjftvn45ukxrpb5jv4

Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs [chapter]

Andres Upegui, Eduardo Sanchez
2005 Lecture Notes in Computer Science  
A modular based evolution, with pre-placed and routed components, provides a coarse grain approach. Two techniques for directly modifying LUT contents on hard macros provide a fine grained evolution.  ...  Finally, integrating both approaches, coarse and fine grain, provides a more general and powerful framework.  ...  Then a partial bitstream, just containing the LUT modifications, will be generated and downloaded to the FPGA.  ... 
doi:10.1007/11549703_6 fatcat:crplzf3qwfdnhbsok3pgkfqghm

FPGA-based high resolution DPWM control circuit

2018 Journal of Systems Engineering and Electronics  
Embedded digital clock manager (DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array (FPGA)-based DPWM implementations.  ...  Two improved structures of high resolution digital pulse width modulator (DPWM) control circuit are proposed.  ...  In particular, two FPGA-based structures for high-resolution DPWM are proposed, where the first approach is also based on DCM, but the RS latch utilized in previous work is replaced by the OR gate which  ... 
doi:10.21629/jsee.2018.06.03 fatcat:3ejp3kpl7fftzizpjnhv7ntlyq

Ternary and Multi-Bit FIR Filter Area-Performance Tradeoffs in FPGA

Khalil-Ur-Rahman Dayo, Tayab Din Memon
2013 Mehran University Research Journal of Engineering and Technology  
Both filters were synthesized on adaptive LUT (Look Up Table) FPGA device in pipelined and non-pipelined modes.  ...  These promising results shows that ternary logic based (i.e. +1,0,-1) filters can be used for huge chip area savings and higher performance.  ...  In this filter design, we have used sigma-delta modulator to generate ternary taps.  ... 
doaj:8a39181bad5f4dad8125fca0e0ccec1b fatcat:7tqhd65ttnaz7b5b74nqn62d6y

Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow

Daisuke SUZUKI, Takahiro HANYU
2021 IEICE transactions on information and systems  
of a CMOS-only volatile FPGA. key words: FPGA, nonvolatile logic, logic synthesis, hardware description language, standard-cell-based design  ...  In this paper, an NV-FPGA is proposed where the programmable logic and interconnect function blocks are described in a hardware description language and are pushed through a standard-cell-based design  ...  Takako of the Focal Agency for his excellent technical assistance.  ... 
doi:10.1587/transinf.2020lop0010 fatcat:jiiluoelnjcntptdqagrl5la7u

BITMAN: A tool and API for FPGA bitstream manipulations

Khoa Dang Pham, Edson Horta, Dirk Koch
2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017  
The functionality includes high-level commands such as cutting out regions of a bitstream and placing or relocating modules on an FPGA as well as low-level commands for modifying primitives and for routing  ...  To fully support the partial reconfiguration capabilities of FPGAs, this paper introduces the tool and API BITMAN for generating and manipulating configuration bitstreams.  ...  However, compared to software development, FPGA development remains too complex. Given a user specification, a stack of transforming tool is executed for generating the bitstream binary for the FPGA.  ... 
doi:10.23919/date.2017.7927114 dblp:conf/date/PhamHK17 fatcat:e6fpjzcsi5b6lab6ckvyklzkem

A Reconfigurable Model-Based Design for Rapid Prototyping on FPGA

Syed Jahanzeb Hussain Pirzada, School of Cyber Science and Technology, Beihang University, Beijing, China, Abid Murtaza, Tongge Xu, Liu Jianwei
2020 Journal of clean energy technologies  
The Model Based Design (MBD) methodology provides a unique methodology for design and implementation of digital systems on Field Programmable Gate Array (FPGA).  ...  Then, a High-Level Synthesis (HLS) is performed on the generated code which converts this high-level code into Verilog-HDL suitable for hardware implementation on FPGA.  ...  LUT Based Implementation The Fig. 3 summarizes LUT based implementation; it involves using phase generation circuit, implemented in the form of accumulator.  ... 
doi:10.7763/ijcte.2020.v12.1268 fatcat:bxch553yerahlp3cl6m7tq73ce

Lookup table partial reconfiguration for an evolvable hardware classifier system

Kyrre Glette, Paul Kaufmann
2014 2014 IEEE Congress on Evolutionary Computation (CEC)  
For demonstration, we rely on a hardware signal classifier application.  ...  Our results show that the proposed approach can fit a classification circuit 4 times larger than an equivalent VRC-based approach, and 6 times larger than a shift registerbased approach, in a Xilinx Virtex  ...  Compared to the SRL-based reconfiguration, which only gives limited access to the FPGA LUTs, partial reconfiguration allows for a full utilization of the FPGA LUT resources, both in terms of the number  ... 
doi:10.1109/cec.2014.6900503 dblp:conf/cec/GletteK14 fatcat:6bs7mzmazjcbdbsuizsebxgkpa

Technique to Dynamically Reconfigure FPGAs using Control Registers

2019 International Journal of Engineering and Advanced Technology  
The proposed control register based architecture was implemented using Cadence Virtuoso using virtual source CNTFET model from Stanford University.  ...  The FPGAs are fault tolerant devices with repetitive structures requiring high packaging density. This property of FPGA enables the use of CNTFETs for design of FPGAs.  ...  Interconnects for Control Register based architecture The FPGA with ARM core and static configurable FPGAs uses ARM AMBA 3.0 AXI protocol for interconnecting all FPGA resources.  ... 
doi:10.35940/ijeat.a1024.1291s319 fatcat:ahmejbptbvgg7gn7od67tjw22i

Real-time OFDM transmitter beyond 100 Gbit/s

R. Schmogrow, M. Winter, D. Hillerkuss, B. Nebendahl, S. Ben-Ezra, J. Meyer, M. Dreschmann, M. Huebner, J. Becker, C. Koos, W. Freude, J. Leuthold
2011 Optics Express  
We demonstrate the potential of the concept by realizing the first real-time single polarization OFDM transmitter generating a 101.5 Gbit/s data stream by modulating 58 subcarriers with 16QAM.  ...  Real-time OFDM transmitters breaking the 100 Gbit/s barrier require high-performance, usually FPGA-based digital signal processing.  ...  Agilent University Relations Program and the German BMBF Project CONDOR.  ... 
doi:10.1364/oe.19.012740 pmid:21716516 fatcat:xt7nrquylvgwhkmb546zrn4uga
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