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Bridging the gap from mask to physical design for multiple patterning lithography
2014
Design-Process-Technology Co-optimization for Manufacturability VIII
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In this paper, we will show some recent results and propose a unified physical design methodology for standard cell compliance, pin access, routing, and placement to bridge the gap from mask/layout decomposition ...
There are many studies on MPL layout decompositions at the mask synthesis stage to resolve the coloring conflicts, minimize the stitches, balance the mask density, or even mitigate the undesirable overlay ...
Acknowledgment This work is supported in part by NSF, SRC, NSFC, IBM and Intel. ...
doi:10.1117/12.2048626
fatcat:ffmkevtekjfmlna7ba4oxhtsme
VLSI Mask Optimization: From Shallow To Deep Learning
[article]
2019
arXiv
pre-print
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In this paper, we focus on a heterogeneous OPC framework that assists mask layout optimization. ...
VLSI mask optimization is one of the most critical stages in manufacturability aware design, which is costly due to the complicated mask optimization and lithography simulation. ...
Ma et al. firstly develops a unified optimization framework which solves layout decomposition and mask optimization simultaneously [17] . ...
arXiv:1912.07254v1
fatcat:x7gt5oobbvb3jhmujrgn6xmxju
Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography
2015
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With the precoloring solutions of standard cells, we present a TPL aware detailed placement where the layout decomposition and placement can be resolved simultaneously. ...
Experimental results show that our framework can achieve zero conflict, meanwhile can effectively optimize the stitch number and placement wire-length. ...
Liebmann at IBM for helpful discussions on this problem. ...
doi:10.1109/tcad.2015.2401571
fatcat:ewfkxenqkfdsloxu4gsgiena44
Methodology for standard cell compliance and detailed placement for triple patterning lithography
2013
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
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With the precoloring solutions of standard cells, we present a TPL aware detailed placement where the layout decomposition and placement can be resolved simultaneously. ...
Experimental results show that our framework can achieve zero conflict, meanwhile can effectively optimize the stitch number and placement wire-length. ...
Liebmann at IBM for helpful discussions on this problem. ...
doi:10.1109/iccad.2013.6691142
dblp:conf/iccad/YuXGP13
fatcat:e5a3fopvuzf3fjks6wgbrx74qm
Design for Manufacturing With Emerging Nanolithography
2013
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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It is essential to have close VLSI design and underlying process technology co-optimization to achieve high product quality (power/performance, etc.) and yield while making future scaling cost-effective ...
Recent results and examples will be discussed to show the enablement and effectiveness of such design and process integration, including lithography model/analysis, mask synthesis, and lithography friendly ...
Liebmann and Dr. R. Puri, IBM, for their helpful discussions. ...
doi:10.1109/tcad.2013.2276751
fatcat:amxc565rjfg6bkliymbbbjczde
Towards Unified Human Parsing and Pose Estimation
2014
2014 IEEE Conference on Computer Vision and Pattern Recognition
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In this work, we propose a unified framework for simultaneous human parsing and pose estimation based on semantic parts. ...
framework via a tailored And-Or graph. ...
Formally, we define the Grid Layout Feature as follows: A) ], where ψ G (A, B) is the GLF between mask A and B. ...
doi:10.1109/cvpr.2014.113
dblp:conf/cvpr/DongCSYY14
fatcat:iptdtb4ptzbfpkmrkqfgmiq4u4
DAMO: Deep Agile Mask Optimization for Full Chip Scale
[article]
2020
arXiv
pre-print
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It is an end-to-end mask optimization paradigm which contains a Deep Lithography Simulator (DLS) for lithography modeling and a Deep Mask Generator (DMG) for mask pattern generation. ...
Moreover, a novel layout splitting algorithm customized for DAMO is proposed to handle the full chip OPC problem. ...
The generality of ILT also enables simultaneous mask optimization and layout decomposition as introduced in [5] . These methods, to some extent, improve OPC from quality, robustness, and efficiency. ...
arXiv:2008.00806v1
fatcat:7oz6nd4w7ve45nw7vd5lsjdygi
Shallow2Deep: Indoor Scene Modeling by Single Image Understanding
2020
Pattern Recognition
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2020 pre-print arXiv:2002.09790v1 fatcat:uxypyt4qjnekbbwqptjnadkcmu
A Relation Network is proposed to infer the support relationship between objects. All the structured semantics and geometry above are assembled to guide a global optimization for 3D scene modeling. ...
Given a single RGB image, our method simultaneously recovers semantic contents, 3D geometry and object relationship by reasoning indoor environment context. ...
project (funded by the Interreg France (Channel) England, ERDF), Innovate UK Smart Grants (39012), the National Natural Science Foundation of China (61702433, 61661146002), the China Scholarship Council and ...
doi:10.1016/j.patcog.2020.107271
fatcat:7cspzpwl2vdm3kipsty5sbmjzq
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict
2017
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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However, MOL layers may introduce a large amount of cross-row TPL conflicts for row based design. ...
. • We carry out a comprehensive study on standard cell level coloring strategy and boolean based look-up table (LUT) ...
ACKNOWLEDGMENT This work is supported in part by NSF and SRC. The authors would like to thank Dr. Yong-Chan Ban at LG Electronics for helpful comments. ...
doi:10.1109/tcad.2017.2648843
fatcat:tim4th4hrfh6nm6feapshandr4
Triple patterning aware detailed placement toward zero cross-row middle-of-line conflict
2015
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
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However, MOL layers may introduce a large amount of cross-row TPL conflicts for row based design. ...
. • We carry out a comprehensive study on standard cell level coloring strategy and boolean based look-up table (LUT) ...
ACKNOWLEDGMENT This work is supported in part by NSF and SRC. The authors would like to thank Dr. Yong-Chan Ban at LG Electronics for helpful comments. ...
doi:10.1109/iccad.2015.7372597
dblp:conf/iccad/LinYXP15
fatcat:btm4muki6rcbnjdibqea4qh6wi
Hypercubic storage layout and transforms in arbitrary dimensions using GPUs and CUDA
2010
Concurrency and Computation
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It also helps transform data between those layouts required for optimum layout in main memory for access by a CPU and the (usually) different optimal layouts in the memory of an accelerator device such ...
We discuss: general memory layouts; specific optimizations possible for dimensions that are powers-of-two and common transformations, such as inverting, shifting and crinkling. ...
ACKNOWLEDGEMENTS Thanks to A. Leist for useful discussions on GPU and CUDA issues. ...
doi:10.1002/cpe.1628
fatcat:fu2k7yxphvck7hx2kiytbqubzi
The engineering design research center of Carnegie Mellon University
1993
Proceedings of the IEEE
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The Center's vision is that a scientific framework for design can explnit rapid adtIances in compUler and communications technolo gies to serve the competitive needfor reduced product development cycles ...
Basic notions of the product cycle underlie the Center's strategic pUPa. a framework of researr:h thrustG leading from barriers in design science 10 goals and vision. ...
rules and an appropriate decomposition for a given task. ...
doi:10.1109/jproc.1993.752023
fatcat:farj3iv5jrfmbbbrgvtptknbwm
Learning Object-Compositional Neural Radiance Field for Editable Scene Rendering
[article]
2021
arXiv
pre-print
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In this paper, we present a novel neural scene rendering system, which learns an object-compositional neural radiance field and produces realistic rendering with editing capability for a clustered and ...
To survive the training in heavily cluttered scenes, we propose a scene-guided training strategy to solve the 3D space ambiguity in the occluded regions and learn sharp boundaries for each object. ...
It is noteworthy that our framework simultaneously learns to encode multiple objects by assigning a bunch of shuffled object activation codes to the training rays, without the need to train for each object ...
arXiv:2109.01847v1
fatcat:ojtf4m7ulnhb7at4tanqd7vf6q
Global and detailed routing
[chapter]
2009
Electronic Design Automation
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We also thank the authors of ] for their help with the formulation of the programming assignment in Exercise 12.11, and Mr. ...
the EDA Laboratory for their very careful review of this chapter. ...
The former adds or subtracts feature patterns to a mask to enhance the layout resolution and thus the printability of the mask patterns on the wafer, whereas the latter improves layout uniformity and chip ...
doi:10.1016/b978-0-12-374364-0.50019-9
fatcat:ybywesjpgjgppotezavllr3vmi
Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs
2010
JSTS Journal of Semiconductor Technology and Science
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A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. ...
As the first result, we found that the optimum ratio of the hardmask oxide thickness (T mask ) to the sidewall oxide thickness (T ox ) is T mask /T ox =10/2 nm for the minimum logic delay (τ) while T mask ...
In this work, motivated by the requirement of the unified design guide for T mask , T ox , H fin , and W fin for the logic gate delay, a comparative study on the trade-off between the drive current and ...
doi:10.5573/jsts.2010.10.2.134
fatcat:xvdeacneirggtin3w5m74smqbu
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