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A fast and low cost testing technique for core-based system-on-chip

Indradeep Ghosh, Sujit Dey, Niraj K. Jha
<span title="">1998</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5vn6yyeefbbxtoo3uhwxwjwtme" style="color: black;">Proceedings of the 35th annual conference on Design automation conference - DAC &#39;98</a> </i> &nbsp;
This paper proposes a new methodology for testing a core-based system-on-chip (SOC), targeting the simultaneous reduction of test area overhead and test application time.  ...  Significant reduction in area overhead and test application time compared to an existing SOC testing technique is also demonstrated.  ...  Acknowledgments: We would like to thank A. Raghunathan for his help with the example embedded systems and NEC CCRL for supporting I. Ghosh with a summer internship.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/277044.277190">doi:10.1145/277044.277190</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dac/GhoshDJ98.html">dblp:conf/dac/GhoshDJ98</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/squmhwp62fdenl7s5m55b6uvee">fatcat:squmhwp62fdenl7s5m55b6uvee</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20010706204504/http://galahad.informatik.tu-chemnitz.de:80/proceedings/dac-98/pdffiles/33_1.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/88/5e/885e31a13638be8ea3d283678997453e8e0ed35c.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/277044.277190"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Test-architecture optimization and test scheduling for SOCs with core-level expansion of compressed test patterns

Anders Larsson, Erik Larsson, Krishnendu Chakrabarty, Petru Eles, Zebo Peng
<span title="">2008</span> <i title="ACM Press"> Proceedings of the conference on Design, automation and test in Europe - DATE &#39;08 </i> &nbsp;
To reduce both test time and test data volume, we propose a technique for test-architecture optimization and test scheduling that is based on core-level expansion of compressed test patterns.  ...  Experimental results for SOCs crafted from several industrial cores demonstrate that the proposed method leads to significant reduction in test data volume and test time, especially when compared to a  ...  We therefore propose a technique where we explore the trade-off between the test time and test data compression at core-level for each core and at SOC-level simultaneously.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1403375.1403422">doi:10.1145/1403375.1403422</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/7um4ryku4zcrvck4iwrbirmmci">fatcat:7um4ryku4zcrvck4iwrbirmmci</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808210606/http://people.ee.duke.edu/~krish/Larsson_DATE2008.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/48/d4/48d43de6581e79660fb85a3746ed3943e633db39.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1403375.1403422"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns

Anders Larsson, Erik Larsson, Krishnendu Chakrabarty, Petru Eles, Zebo Peng
<span title="">2008</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qjrrvry5ubgdlarkymvlxuip6m" style="color: black;">2008 Design, Automation and Test in Europe</a> </i> &nbsp;
To reduce both test time and test data volume, we propose a technique for test-architecture optimization and test scheduling that is based on core-level expansion of compressed test patterns.  ...  Experimental results for SOCs crafted from several industrial cores demonstrate that the proposed method leads to significant reduction in test data volume and test time, especially when compared to a  ...  We therefore propose a technique where we explore the trade-off between the test time and test data compression at core-level for each core and at SOC-level simultaneously.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2008.4484684">doi:10.1109/date.2008.4484684</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/date/LarssonLCEP08.html">dblp:conf/date/LarssonLCEP08</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/gbtl6wqbnfcmxpepsxt23iwli4">fatcat:gbtl6wqbnfcmxpepsxt23iwli4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808210606/http://people.ee.duke.edu/~krish/Larsson_DATE2008.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/48/d4/48d43de6581e79660fb85a3746ed3943e633db39.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2008.4484684"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs

Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Richard Kacprowicz
<span title="">2008</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qjrrvry5ubgdlarkymvlxuip6m" style="color: black;">2008 Design, Automation and Test in Europe</a> </i> &nbsp;
A secondary objective is to minimize the test application time. Simulation results are presented for two ITC'02 SoC benchmarks, and the proposed technique is compared with two baseline methods.  ...  Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing.  ...  Results for two ITC'02 SoC test benchmarks show that a significant reduction in power variation is obtained using the proposed method. Fig. 1 . 1 (a) TAM architecture for the d695 SoC with W = 32.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2008.4484925">doi:10.1109/date.2008.4484925</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/date/BahukudumbiCK08.html">dblp:conf/date/BahukudumbiCK08</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/irwksuhr7reqpmqpnc2vc2biwa">fatcat:irwksuhr7reqpmqpnc2vc2biwa</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20081002140317/http://www.ee.duke.edu/~krish/Bahukudumbi_DATE2008.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/14/f1/14f128f115a02ea493d23971ddf455ae02be7863.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2008.4484925"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Test scheduling for wafer-level test-during-burn-in of core-based SoCs

Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Richard Kacprowicz
<span title="">2008</span> <i title="ACM Press"> Proceedings of the conference on Design, automation and test in Europe - DATE &#39;08 </i> &nbsp;
A secondary objective is to minimize the test application time. Simulation results are presented for two ITC'02 SoC benchmarks, and the proposed technique is compared with two baseline methods.  ...  Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing.  ...  Results for two ITC'02 SoC test benchmarks show that a significant reduction in power variation is obtained using the proposed method. Fig. 1 . 1 (a) TAM architecture for the d695 SoC with W = 32.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1403375.1403640">doi:10.1145/1403375.1403640</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/zknv3uv2vvgplb6qwhbmasw65u">fatcat:zknv3uv2vvgplb6qwhbmasw65u</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20081002140317/http://www.ee.duke.edu/~krish/Bahukudumbi_DATE2008.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/14/f1/14f128f115a02ea493d23971ddf455ae02be7863.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1403375.1403640"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

SmartScan - Hierarchical test compression for pin-limited low power designs

K. Chakravadhanula, V. Chickermane, D. Pearl, A. Garg, R. Khurana, S. Mukherjee, P. Nagaraj
<span title="">2013</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/c6t4qycpy5haxkpjvywsoox6dq" style="color: black;">2013 IEEE International Test Conference (ITC)</a> </i> &nbsp;
When multiple cores are embedded in a SoC with limited tester-contacted pins, there is a need for a structured test-access mechanism (TAM) architecture that allows compressed test data stimuli and responses  ...  This paper presents SmartScan, a TAM architecture that is based on time-domain multiplexing of compressed data.  ...  Acknowledgements The authors would like to acknowledge and thank Jordy Asher, Brion Keller, Ripu Singh, Rick Schoonover, Leon Palmer and Balveer Koranga for their valuable contributions to this work.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/test.2013.6651897">doi:10.1109/test.2013.6651897</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/itc/ChakravadhanulaCPGKMN13.html">dblp:conf/itc/ChakravadhanulaCPGKMN13</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/qcvljrq26jexzb3jeq7s7aus6i">fatcat:qcvljrq26jexzb3jeq7s7aus6i</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170818090642/https://www.computer.org/csdl/proceedings/itc/2013/9999/00/06651897.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/2c/25/2c25920fd63e4422970ac74c10aa95b8239fbe61.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/test.2013.6651897"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling

Quming Zhou, Kedarnath J. Balakrishnan
<span title="">2007</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qjrrvry5ubgdlarkymvlxuip6m" style="color: black;">2007 Design, Automation &amp; Test in Europe Conference &amp; Exhibition</a> </i> &nbsp;
By using the combined approach, the total test data volume and test application time of the SoC is reduced to a level comparable with the test data volume and test application time of the largest core  ...  A combined approach for implementing system level test compression and core test scheduling to reduce SoC test costs is proposed in this paper.  ...  As can be seen from the table, proposed scheme achieves very good test data volume and test application time reduction.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2007.364564">doi:10.1109/date.2007.364564</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/date/ZhouB07.html">dblp:conf/date/ZhouB07</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/6zggvakqerdiflgwvtb47okhum">fatcat:6zggvakqerdiflgwvtb47okhum</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170922004844/https://www.date-conference.com/proceedings-archive/PAPERS/2007/DATE07/PDFFILES/01.3_3.PDF" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/5f/bc/5fbce5eb1f2034e74da32a8c092894ec3362d17e.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2007.364564"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs

Anuja Sehgal, Krishnendu Chakrabarty
<span title="">2007</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5jlmyrayyrdazh5awdlsoec77q" style="color: black;">IEEE transactions on computers</a> </i> &nbsp;
Therefore, we formulate the following optimization problem: Given two available data rates for the tester channels, an SOC-level test access mechanism (TAM) width W , an upper limit V ðV < WÞ on the number  ...  We present an efficient heuristic algorithm for TAM optimization that exploits port scalability of ATEs to reduce SOC testing time and test cost.  ...  A preliminary version of this paper appeared in the Proceedings of the IEEE Design, Automation and Test in Europe (DATE) Conference, pp. 422-427, 2004.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tc.2007.250628">doi:10.1109/tc.2007.250628</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/5aplodnpzneufb5zpbthrmvhgy">fatcat:5aplodnpzneufb5zpbthrmvhgy</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170830055636/http://people.ee.duke.edu/~krish/Sehgal_TC_2007.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/a2/73/a27366510ce1c6845770b7aeaedaf2bd51af326b.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tc.2007.250628"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

A New Multi-site Test for System-on-Chip Using Multi-site Star Test Architecture

Dongkwan Han, Yong Lee, Sungho Kang
<span title="2014-04-01">2014</span> <i title="Wiley"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/sfkftjpfyneypmldn7no2ilfpm" style="color: black;">ETRI Journal</a> </i> &nbsp;
Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.  ...  To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design.  ...  Another advantage is that a high test cost reduction and test time reduction can be achieved since the bandwidth required for the interface between the ATE and one DUT is dramatically reduced.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.4218/etrij.14.0113.0469">doi:10.4218/etrij.14.0113.0469</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/lu65cekz4rabfpsluzqiw7r4ty">fatcat:lu65cekz4rabfpsluzqiw7r4ty</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170705090858/http://soc.yonsei.ac.kr/Abstract/International_journal/pdf/no_115.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/cb/aa/cbaafb7e4b787d10b46927a78031332da060fa00.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.4218/etrij.14.0113.0469"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> Publisher / doi.org </button> </a>

Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips

A. Sehgal, S.K. Goel, E.J. Marinissen, K. Chakrabarty
<span title="">2006</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qjrrvry5ubgdlarkymvlxuip6m" style="color: black;">Proceedings of the Design Automation &amp; Test in Europe Conference</a> </i> &nbsp;
We investigate hierarchy-aware test infrastructure design, wherein wrapper/TAM optimization and test scheduling are carried out for hierarchical SOCs for two practical design scenarios.  ...  Experimental results are presented for the ITC'02 SOC test benchmarks.  ...  IfC i is a hierarchical (parent) core, the test data for it also includes the test data and test infrastructure parameters for its child cores.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2006.244140">doi:10.1109/date.2006.244140</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/date/SehgalGMC06.html">dblp:conf/date/SehgalGMC06</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/2koaykms4zaw3o22edswrpxg34">fatcat:2koaykms4zaw3o22edswrpxg34</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20060907101614/http://www.ee.duke.edu/~krish/03C_1.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/56/38/563847f9938ef97d4e9a91da735b3f7260b374f3.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2006.244140"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Resource-constrained system-on-a-chip test: a survey

Q. Xu, N. Nicolici
<span title="">2005</span> <i title="Institution of Engineering and Technology (IET)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/i6gaqnnagndt7pf6mxgezspaka" style="color: black;">IEE Proceedings - Computers and digital Techniques</a> </i> &nbsp;
In addition, when addressing these new challenges, the SOC designers must consciously use the resources at hand, while keeping the testing time and volume of test data under control.  ...  With the ongoing shift towards the core-based system-on-a-chip (SOC) design paradigm, unique test challenges, such as test access and test reuse, are confronted.  ...  Within a satisfactory test development time (C prep ), the main source of SOC test cost reduction lies in the reduction of C exec and C silicon .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1049/ip-cdt:20045019">doi:10.1049/ip-cdt:20045019</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/6ofceww26veufioqaq2wjhpnem">fatcat:6ofceww26veufioqaq2wjhpnem</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170706075017/http://www.cse.cuhk.edu.hk/~qxu/xu-cdt05.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/67/41/67412fba35bf54ef6085a6ca4e63fdc4fd33afc0.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1049/ip-cdt:20045019"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

A unified approach to reduce soc test data volume, scan power and testing time

A. Chandra, K. Chakrabarty
<span title="">2003</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/rl7xk4fwazdrred2difr6v3lii" style="color: black;">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</a> </i> &nbsp;
We present a test resource partitioning (TRP) technique that simultaneously reduces test data volume, test application time, and scan power.  ...  Experimental results for the larger ISCAS89 benchmarks and an IBM production circuit show that reduced test data volume, test application time, and low power-scan testing can indeed be achieved in all  ...  Keller of Cadence Design Systems, Endicott, NY, (formerly with IBM Corporation, Endicott, NY), for providing scan vectors for the production circuit.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcad.2002.807895">doi:10.1109/tcad.2002.807895</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/6fq7eyn4b5foxhjfi6fkn23j24">fatcat:6fq7eyn4b5foxhjfi6fkn23j24</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170810121242/http://people.ee.duke.edu/~krish/TCAD03_03_Chandra.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/84/ef/84ef01b840da33e63c284a61a940c4b0cbf4c038.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcad.2002.807895"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Zhanglei Wang, K. Chakrabarty, Seongmoon Wang
<span title="">2009</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/rl7xk4fwazdrred2difr6v3lii" style="color: black;">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</a> </i> &nbsp;
We present a system-on-chip (SOC) testing approach that integrates test data compression, test-access mechanism/test wrapper design, and test scheduling.  ...  At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the care bits for the test cubes for multiple cores.  ...  Compared with the dynamic ATPG test patterns, the dynamic method achieves 6.37× and 5.71× reduction in test data volume (equal to TD/TE) for the two reported cases (S max = 64 and S max = 128).  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcad.2009.2021731">doi:10.1109/tcad.2009.2021731</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/tegxogeexzeybaxkseq6ic4jsi">fatcat:tegxogeexzeybaxkseq6ic4jsi</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20100619105712/http://people.ee.duke.edu/~krish/tcad2009_wang.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/d9/17/d9171f0448dc6c7191c863e2e010ca52ed26e588.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcad.2009.2021731"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

System-on-Chip Power Consumption Refinement and Analysis

David Y. Feinstein, Mitchell A. Thornton, Fatih Kocan
<span title="">2007</span> <i title="IEEE"> 2007 6th IEEE Dallas Circuits and Systems Workshop on System-on-Chip </i> &nbsp;
We present a demonstration tool for continuous logging of the instantaneous power consumption with an identification of the running process within the SoC.  ...  Accurate power consumption estimation of a System-on-Chip (SoC) using modeling techniques is difficult due to the diverse mixture of processes with radically different current consumption.  ...  Their paper covered traditional power consumption reduction techniques based on voltage scaling, frequency reduction and leakage current minimization.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dcas.2007.4433204">doi:10.1109/dcas.2007.4433204</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/mtncgt5dyrdzzcqdb3ivj7raze">fatcat:mtncgt5dyrdzzcqdb3ivj7raze</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20080221190414/http://engr.smu.edu/~mitch/ftp_dir/pubs/dcas07.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/1d/21/1d21146465b3b3890ad0f22d47522143939a9a53.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dcas.2007.4433204"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Advancements regarding in-operando diagnosis techniques for solid oxide cells NiYSZ cermets

A. Baldinelli, L. Barelli, G. Bidini, A. Di Cicco, R. Gunnella, M. Minicucci, A. Trapananti
<span title="">2019</span> <i title="AIP Publishing"> SECOND INTERNATIONAL CONFERENCE ON MATERIAL SCIENCE, SMART STRUCTURES AND APPLICATIONS: ICMSS-2019 </i> &nbsp;
This review aims at presenting the advantages of in-situ and in-operando diagnosis techniques for the detection of specific degradation mechanisms affecting SOC cermets.  ...  Development of an analytical model to investigate the effects of the extraflux versus the sky and the ground and optimization of the radiative characteristics of a thermochromic paint for a typical Italian  ...  These kinds of characterization are widespread for a matter of simplicity regarding both the technique itself (sensors, data sampling, data analysis) and the realization of a proper experimental setup.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1063/1.5138745">doi:10.1063/1.5138745</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/t2pxinnvsjho5jwjomccq6f3ju">fatcat:t2pxinnvsjho5jwjomccq6f3ju</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20210428160726/https://pubblicazioni.unicam.it/retrieve/handle/11581/437071/134817/Baldinelli-1.5138745.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/14/7b/147be071f386662d7c506bc451d123f4af664f4c.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1063/1.5138745"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>
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