345 Hits in 6.0 sec

Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers

Syed Ahmed Aamir, Prakash Harikumar, J. Jacob Wikner
2013 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)  
A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process.  ...  The three-stage OTA with RNIC achieves PM of 81 • , DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59 • with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz.  ...  In this work, a three-stage OTA has been designed in a 1.1-V, 40-nm CMOS process.  ... 
doi:10.1109/iscas.2013.6571860 dblp:conf/iscas/AamirHW13 fatcat:sryuph5ujfdstctex5fbe2ddti

Design of DC-DC Boost Converter in CMOS 0.18μm Technology

M. Rama Devi, R. Sunil Kumar, M. Madhava Kumar
2016 International Journal of Computer Engineering in Research Trends  
A CMOS DC-DC boost converter with fastest settling time and less quiescent current with a feedback control is implemented.  ...  With a wide range of loads, it provides 25V at the output, 50mA load current with 90% efficiency.  ...  For dynamic response consideration, pole-zero cancellation is preferable to dominant pole compensation as the bandwidth can be extended with pole-zero cancellation to speed up the response time.  ... 
doi:10.22362/ijcert/2016/v3/i10/48905 fatcat:fkwtgzhkujhkfd6i73cuq3amwy

A high gain, wide-band, fast settling amplifier with no-miller capacitor compensation

Soroush Moallemi, Abumoslem Jannesari
2011 IEICE Electronics Express  
Also, a new technique for pole zero cancellation in three-stage OTAs is presented. The proposed OTA simulated in standard TSMC 0.18 μm CMOS technology with a 1.8 V power supply.  ...  A high DC gain, wide band and fast settling fully differential amplifier is presented. The pole zero cancellation technique is used in order to increase the band width of the OTA.  ...  The total OTA is simulated with standard TSMC 0.18 μm CMOS technology with 1.8 V power supply using the Hspice circuit simulator. The output common mode voltage is set to 0.9 V Fig. 2 a.  ... 
doi:10.1587/elex.8.1751 fatcat:omkp2bwrgndkdmcsqux5e5shl4

A 10.7-MHz sixth-order SC ladder filter in 0.35-/spl mu/m CMOS technology

J. Adut, J. Silva-Martinez, M. Rocha-Perez
2006 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
The chip was fabricated in a 0.35m CMOS process; filter's area is 0.84 mm 2 .  ...  The filter uses a multipath operational transconductance amplifier (OTA) that presents both better accuracy and higher slew rate than previously reported Class-A OTA topologies.  ...  The dc gain is similar to the one obtained with a two-stage amplifier and it is extremely efficient in terms of static power and PM; comparisons between folded-cascode and telescopic amplifiers have been  ... 
doi:10.1109/tcsi.2006.879070 fatcat:rlwaxzkrnbfllooqnrhcn3tqvy

Review of CMOS Amplifiers for High Frequency Applications

2020 International Journal of Engineering and Advanced Technology  
A lot of amplifier topologies are experimented and discussed in the literature with its design and simulation.  ...  In this paper, the various efforts associated with CMOS amplifier circuit for high-frequency applications are studying extensively.  ...  In the same year, J.A.Fisher proposed a CMOS Power Amplifier with new input stage with a modified class AB output stage [7] .  ... 
doi:10.35940/ijeat.b2101.1210220 fatcat:nqoamtzqlfdg3dwip2hy6ola2q

A 0.4 V Bulk-Driven Amplifier for Low-Power Data Converter Applications

R. Rezaei, A. Ahmadpour, M. N. Moghaddasi
2013 Circuits and Systems  
The stability condition of this structure for the DC gain is considered by definition of two coefficients to cancel out a controllable percentage of the denominator.  ...  The designed P-OTA have a DC gain of 64 dB, 212 KHz unity gain bandwidth, 57˚ phase margin that is loaded by 10 pF differential capacitive loads, while consume only 16 µW.  ...   1 o C R C  1 c    Figure 1 . 1 Proposed P-OTA: (a) One stage of the P-OTA; (b) AC model of the P-OTA; (c) Two-stage P-OTA with miller compensations.  ... 
doi:10.4236/cs.2013.41016 fatcat:i764tyxdn5eklasabdb6ljl34a

Chopping-Out-Of-band (COOB) for reducing ripple in chopper amplifiers

Tong Ling, Huajun Fang, Xiao Zhao, Jun Xu
2015 IEICE Electronics Express  
By choosing a suitable chopping frequency ( f chop ) located in GBW < f chop < NLBW (No-Load Bandwidth), the ripple will be suppressed rather than amplified and the effect can be improve further by an  ...  These chopper amplifiers were simulated on UMC 0.18 um technology with the help of Cadence SpectreRF.  ...  Simulation results Two instrumentation amplifiers AMP1 and AMP2 were designed shown in Fig. 5(a) and (b), and the amplifiers were simulated on UMC 0.18 um CMOS process with the help of spetreRF.  ... 
doi:10.1587/elex.12.20141226 fatcat:qii5eik2hjdtjejiepoc7cxy6u

A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors

B.K. Thandri, J. Silva-Martinez
2003 IEEE Journal of Solid-State Circuits  
A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster.  ...  Experimental results for a prototype fabricated in AMI 0.5m CMOS process show dc gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is 1.25 V.  ...  (a) Perfect pole-zero cancellation. (b) Pole-zero mismatch.  ... 
doi:10.1109/jssc.2002.807410 fatcat:j64oig4v4nglff2mu2ozyj62q4

High-Speed High-Gain Cmos Ota For Sc Applications

M.Yousefi, A.Vatanjou, F.Nazeri
2012 Zenodo  
A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here.  ...  With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to output.  ...  and folded-cascode OTA have been m standard CMOS technology and simulated with HSPICE software.  ... 
doi:10.5281/zenodo.1081897 fatcat:orhkqp76yzcjrh3cf6chglvjnq

An Integrated CMOS Bio-potential Amplifier with a Feed-Forward DC Cancellation Topology

Jayant Parthasarathy, Arthur G. Erdman, Aaron D. Redish, Babak Ziaie
2006 2006 International Conference of the IEEE Engineering in Medicine and Biology Society  
This paper describes a novel technique to realize an integrated CMOS bio-potential amplifier with a feedforward DC cancellation topology.  ...  Measurement results show a gain of 43.5dB in the pass band (<1mHz-5KHz), an input referred noise of 3.66 A.  ...  A suitable Operational Amplifier could substitute the OTA if the circuit is driving resistive loads.  ... 
doi:10.1109/iembs.2006.259577 pmid:17945749 fatcat:bx6oldcikjaljn2bzkw4l53a3e

Low-Power Architecture and Circuit Techniques for High-Boost Wide-Band $G_m$–$C$ Filters

Manisha Gambhir, Vijay Dhanasekaran, Jose Silva-Martinez, Edgar Snchez-Sinencio
2007 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
A prototype is fabricated in a standard 0.35-m CMOS process. Experimental results show 41 dB of IM3 for 250-mV peak-peak swing with 43 mW of power dissipation.  ...  The proposed solution realizes two symmetric real axis zeros by efficiently combining transfer functions associated with all nodes of cascaded biquad cells.  ...  The CMOS OTA can be viewed as a nMOS OTA connected in parallel with a pMOS OTA; so as to facilitate reuse of bias current.  ... 
doi:10.1109/tcsi.2006.887633 fatcat:zu6dc22ygjcltfjvp6zrruzkqu

Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS

Prakash Harikumar, J Jacob Wikner
2015 2015 IEEE International Symposium on Circuits and Systems (ISCAS)  
The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages.  ...  using a three-stage OTA designed in 40 nm CMOS.  ...  In a two-stage Miller compensated OTA, the non-dominant pole is formed at the output nodes.  ... 
doi:10.1109/iscas.2015.7168617 dblp:conf/iscas/HarikumarW15 fatcat:vedlais3pfdh3j3liiohu73lxy

A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

Francesco Centurelli, Riccardo Della Sala, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
2021 Journal of Low Power Electronics and Applications  
In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power  ...  The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal  ...  The OTA presented in this paper has a common-mode cancelling bodydriven input stage with a body-diode load, which produces a high-frequency pole, followed by a differential-to-single-ended converter, without  ... 
doi:10.3390/jlpea11020019 fatcat:sgtjnyqrafc2diyriqdqwudcgm

Analog CMOS peak detect and hold circuits. Part 2. The two-phase offset-free and derandomizing configuration

Gianluigi De Geronimo, Paul O'Connor, Anand Kandasamy
2002 Nuclear Instruments and Methods in Physics Research Section A : Accelerators, Spectrometers, Detectors and Associated Equipment  
It is based on a configuration that cancels the major error sources of the classical CMOS PDH, including offset and common mode gain, by re-using the same amplifier for tracking, peak sensing, and output  ...  The first experimental results on the new peak detector and derandomizer (PDD) circuit, fabricated in 0.35 mm CMOS technology, include a 0.2% absolute accuracy for pulses with 500 ns peaking time, 2.7  ...  Radeka (BNL) and A. Hrisoho (LAL, Orsay) for help and encouragement with this project and John Triolo for the technical assistance.  ... 
doi:10.1016/s0168-9002(01)02060-5 fatcat:jga2zsrtmnhpxdbwplbpbqylkm

A Monolithic Current-Mode CMOS DC–DC Converter With On-Chip Current-Sensing Technique

C.F. Lee, P.K.T. Mok
2004 IEEE Journal of Solid-State Circuits  
A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this paper.  ...  The output ripple voltage is about 20 mV with a 10-F off-chip capacitor and 4.7-H off-chip inductor. The power efficiency is over 80% for load current from 50 to 450 mA.  ...  Cascode OTA For the power stage of current-mode converters, the control-to-output transfer function has two separated real poles as described in [7] - [9] .  ... 
doi:10.1109/jssc.2003.820870 fatcat:vypfi4i3yrebbia4t7y6sug3ci
« Previous Showing results 1 — 15 out of 345 results