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Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method

Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2005 IEEE transactions on circuits and systems for video technology (Print)  
The other two proposed architectures are for multi-level decomposition.  ...  In this paper, three generic RAM-based architectures are proposed to efficiently construct the corresponding two-dimensional architectures by use of the line-based method for any given hardware architecture  ...  His major research interests include VLSI design and implementation for 1-D, 2-D, and 3-D discrete wavelet transform.  ... 
doi:10.1109/tcsvt.2005.848307 fatcat:byafnytpazcn7llxaf5e6nwvvu

Memory-efficient architecture for JPEG 2000 coprocessor with large tile image

Bing-Fei Wu, Chung-Fu Lin
2006 IEEE Transactions on Circuits and Systems - II - Express Briefs  
For example, it would require tile memory of 256 K words to support the process of a 512 512 tile image in the straightforward architecture.  ...  However, processing large tile images also requires relatively high memory for the hardware implementation.  ...  Based on the better coding efficiency for processing large tile images, it is a reasonable demand to design the hardware architecture to support large tile sizes.  ... 
doi:10.1109/tcsii.2005.862042 fatcat:z2rvkybcjjby3ioz64bu6uawhq

Two-Level Scratchpad Memory Architectures to Achieve Time Predictability and High Performance

Yu Liu, Wei Zhang
2014 Journal of Computing Science and Engineering  
Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks  ...  This paper proposes a time-predictable twolevel scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing.  ...  To combine the advantages of both SPMs and two-level architectures for balancing access latency and capacity, we propose a two-level SPM-based architecture for realtime systems, as shown in Fig. 2 .  ... 
doi:10.5626/jcse.2014.8.4.215 fatcat:my6zstv7lndtvoj3bng7gb7c2e

Advances in Hardware Architectures for Image and Video Coding - A Survey

Po-chih Tseng, Yung-chi Chang, Yu-wen Huang, Hung-chi Fang, Chao-tsung Huang, Liang-gee Chen
2005 Proceedings of the IEEE  
This paper provides a survey of state-of-the-art hardware architectures for image and video coding.  ...  Further perspectives are also presented to address the challenges of hardware architecture design for advanced image and video coding in the future.  ...  As image and video coding algorithms involve a large amount of data computation, during processing continuous data streams in huge volumes, a large amount of data communication is also incurred in two  ... 
doi:10.1109/jproc.2004.839622 fatcat:bew6snuhhnhuhedezd7x5wojqu

Stream Execution on Embedded Wide-Issue Clustered VLIW Architectures

Shan Yan, Bill Lin
2008 EURASIP Journal on Embedded Systems  
Existing compilation approaches for clustered-VLIW architectures are based on extensions of previously developed scheduling algorithms that primarily focus on the maximization of instruction-level parallelism  ...  Advances in clustered VLIW architectures have extended the scalability of the VLIW architecture paradigm to a large number of functional units and very-wide-issue widths.  ...  ACKNOWLEDGMENTS We would like to acknowledge Alan Gatherer and David Hoyle from Texas Instruments, Inc. for a number of stimulating discussions on both application and compiler requirements for wide-issue  ... 
doi:10.1155/2008/516240 fatcat:5bknozgbyvc7pkuowofzewowje


Mehrdad Moradi, Li Erran Li, Z. Morley Mao
2014 Proceedings of the third workshop on Hot topics in software defined networking - HotSDN '14  
Indeed, a logically-centralized controller in one pointof-presence with a flat architecture quickly becomes infeasible, if the mobile WAN spans a large region.  ...  The current 4G LTE network architecture is organized into very large and rigid regions, each with an access edge consisting of only base stations and an Internet edge comprised of centralized packet gateways  ...  For the rest of the paper, we explain our architecture with two hierarchical levels.  ... 
doi:10.1145/2620728.2620763 dblp:conf/sigcomm/MoradiLM14 fatcat:shef2f2embeellrl72km3ejgra

Exploiting SPM-aware Scheduling on EPIC architectures for high-performance real-time systems

Yu Liu, Wei Zhang
2012 2012 IEEE Conference on High Performance Extreme Computing  
Based on the EPIC, this paper proposes a time predictable two-level scratchpad based memory architecture, and a Scratchpad-aware Scheduling method to improve the performance by optimizing the Load-To-Use  ...  In contemporary computer architectures, the Explicitly Parallel Instruction Computing Architectures (EPIC) permits microprocessors to implement Instruction Level Parallelism (ILP) by using the compiler  ...  SCRATCHPAD MEMORIES To combine the advantages of both scratchpad memories and two-level architectures, we propose a two-level scratchpad based architecture on the EPIC microprocessors for real-time systems  ... 
doi:10.1109/hpec.2012.6408658 dblp:conf/hpec/Liu012 fatcat:umhe577lo5hctk77fr6lglrpsi

Data Packet Processing Model based on Multi-Core Architecture

Xian Zhang
2018 International Journal of Performability Engineering  
The principle of a tree-based parallel architecture model is to use pipelining and flow-pinning technology to design a processor that is specifically used to capture data packets, and other processors  ...  are responsible for other stages of parallel processing of the data packets.  ...  It can be seen that, for a large number of TCP connections, the tree-based parallel architecture model has a much higher throughput than the horizontal-based parallel architecture model (more than 6X greater  ... 
doi:10.23940/ijpe.18.07.p1.13831390 fatcat:4flik2anyjf2bjaomndflc3che

A Survey on Lifting-based Discrete Wavelet Transform Architectures

Tinku Acharya, Chaitali Chakrabarti
2006 Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology  
In this paper, we provide a survey of these architectures for both 1-dimensional and 2-dimensional DWT.  ...  In this paper, we review recent developments in VLSI architectures and algorithms for efficient implementation of lifting based Discrete Wavelet Transform (DWT).  ...  We provided a systematic derivation of each architecture and evaluated them with respect to their hardware and timing requirements.  ... 
doi:10.1007/s11266-006-4191-3 fatcat:44q5xd3d4nba5ccjukfvcfhnvq

Using Multi-Core HW/SW Co-design Architecture for Accelerating K-means Clustering Algorithm [article]

Hadi Mardani Kamali
2018 arXiv   pre-print
In this paper, we demonstrate that using a two-level filtering algorithm based on binary kd-tree structure is able to decrease the time of convergence in K-means algorithm for large datasets.  ...  The empirical result on this two-level structure over multi-core FPGA-based architecture provides 330X speed-up compared to a conventional software-only solution.  ...  HW/SW CO-DESIGN TWO-LEVEL K-MEANS CLUSTERING Similar to [6, 9, 22, 23, 17] , we demonstrate that MUCH-SWIFT [27] , as a HW/SW co-design architecture, accelerates k-means algorithm by using a system-level  ... 
arXiv:1807.09250v1 fatcat:wbvre7jsbbgxtjlcilfwfvpqv4

Hierarchical Deep Learning Architecture For 10K Objects Classification [article]

Atul Laxman Katole, Krishna Prasad Yellapragada, Amish Kumar Bedi, Sehaj Singh Kalra, Mynepalli Siva Chaitanya
2015 arXiv   pre-print
We propose a two level hierarchical deep learning architecture inspired by divide & conquer principle that decomposes the large scale recognition architecture into root & leaf level model architectures  ...  The proposed architecture classifies objects in two steps. In the first step the root level model classifies the object in a high level category.  ...  Shankar M Venkatesan for his guidance and constant encouragement. Without his support it would not have been possible to materialize this paper.  ... 
arXiv:1509.01951v1 fatcat:zm6636eulfgcpgn3qgai36tpke

High-level interconnect model for the quantum logic array architecture

Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross, Isaac L. Chuang, Frederic T. Chong
2008 ACM Journal on Emerging Technologies in Computing Systems  
The design goal of the the quantum logic array architecture is to illustrate a model for a large-scale quantum architecture that solves the primary challenges of system-level reliability and data distribution  ...  Our physical-level assumptions and architectural component validations are based on the trapped ion technology for implementing quantum computing.  ...  Based on the circuit model of computation [Deutsch 1985 ], we identified three main scalability issues for building a large-scale quantum architecture, as next described. (1) Availability of reliable  ... 
doi:10.1145/1330521.1330522 fatcat:pz3wuk4qwnbplpzksc7pzqgj24

A C-Based Variable Length and Vector Pipeline Architecture Design Methodology and Its Application

Takashi Kambe, Nobuyuki Araki
2012 Circuits and Systems  
In this paper, we propose a C-based variable length and vector pipeline (VVP) architecture design methodology and apply it to the design of the output probability computation circuit for a speech recognition  ...  It is shown that designers can explore a wide range of design choices and generate complex circuits in a short time by using a C-based pipeline architecture design method.  ...  Acknowledgements The authors would like to thank the Bach system development group in SHARP Corporation Electronic Components and Devices Development Group, for their help in hardware design using the  ... 
doi:10.4236/cs.2012.31002 fatcat:5dq4iehh4zcovmekv3i5ijyvne

On Creating Industry-Wide Reference Architectures

Liming Zhu, Mark Staples, Vladimir Tosic
2008 2008 12th International IEEE Enterprise Distributed Object Computing Conference  
To achieve the right level of prescriptiveness, our reference architectures are deliberately non-structural. Instead, they are based on a set of quality-centric architectural rules.  ...  Such data-only standards leave a very large interpretation space for the implementation stage at each individual organization. Thus, true industry-wide interoperability is still hard to achieve.  ...  data level) interoperability.  ... 
doi:10.1109/edoc.2008.14 dblp:conf/edoc/ZhuST08 fatcat:c74nohevyzdtrdhbznm4t3tjqy

Comparison between the Simulator and Scheduler based approach of Design Space Exploration for Application Specific Instruction set Processor

M. K.Jain, Deepak Gour
2012 International Journal of Computer Applications  
An Application Specific Instruction set Processor (ASIP) is a processor designed for a particular application or for a set of applications.  ...  ASIP Design Space Exploration can be carried out by one of the two popular available techniques as Simulator or Scheduler based approach.  ...  The approach has been validated on two different parameterized architectures: one based on a RISC processor and another based on a parameterized very long instruction word architecture.  ... 
doi:10.5120/6098-8290 fatcat:p2byhxibpzc77fu37s7z57rmny
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