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A Theoretical Upper Bound for IP-Based Floorplanning
[chapter]
2005
Lecture Notes in Computer Science
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Floorplan is a crucial estimation task in the modern layout design of systems on chips. The paper presents a novel theoretical upper bound for slicing floorplans with soft modules. ...
We show that, given a set of soft modules of total area A total , maximum area A max , and shape flexibility r ≥ 2.25, there exists a slicing floorplan F of these modules such that Area(F) ≤ min{1.131, ...
Conclusion We presented a theoretical upper bound for slicing floorplans with soft rectangles. ...
doi:10.1007/11533719_42
fatcat:ozwnq4uh6rauda4lmdyhlagwki
Optimal slack-driven block shaping algorithm in fixed-outline floorplanning
2012
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design - ISPD '12
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Given a fixed upper bound on the layout width, SDS minimizes the layout height by only shaping the soft blocks in the design. ...
Different from all previous approaches, SDS is specifically formulated for fixed-outline floorplanning. ...
Zhou from Northwestern University for providing us the source code of algorithms [11] and [12] . ...
doi:10.1145/2160916.2160956
dblp:conf/ispd/YanC12
fatcat:tynmb4jgqjebtjuljg4k77iizq
Fast floorplanning by look-ahead enabled recursive bipartitioning
2005
Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05
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A new paradigm is introduced for floorplanning any combination of fixed-shape and variable-shape blocks under tight fixedoutline area constraints and a wirelength objective. ...
Dramatic improvement over traditional floorplanning methods is achieved by explicit construction of strictly legal layouts for every partition block at every level of a cutsize-driven, top-down hierarchy ...
Previous work on this subject either analyzed the theoretical upper bounds on the total area achieved by slicing floorplans of soft blocks [22] , [32] or generate zero-dead-space floorplans with no ...
doi:10.1145/1120725.1120838
dblp:conf/aspdac/CongRS05
fatcat:o6du4ctb2bdhnlqakplpnfk7jy
Fast floorplanning by look-ahead enabled recursive bipartitioning
2006
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A new paradigm is introduced for floorplanning any combination of fixed-shape and variable-shape blocks under tight fixedoutline area constraints and a wirelength objective. ...
Dramatic improvement over traditional floorplanning methods is achieved by explicit construction of strictly legal layouts for every partition block at every level of a cutsize-driven, top-down hierarchy ...
Previous work on this subject either analyzed the theoretical upper bounds on the total area achieved by slicing floorplans of soft blocks [22] , [32] or generate zero-dead-space floorplans with no ...
doi:10.1109/tcad.2005.859519
fatcat:4gtdaralfveo3nvrpkz3i57p2u
Assembling 2D blocks into 3D chips
2011
Proceedings of the 2011 international symposium on Physical design - ISPD '11
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In part, this is due to the wide availability of trustworthy intellectual property (IP) blocks developed for 2D ICs and proven through repeated use. ...
Block-based design reuse is imperative for heterogeneous 3D ICs where memory, logic, analog and micro-electro-mechanical systems (MEMS) dies are manufactured at different technology nodes and circuit modules ...
Therefore, we wrap our methodology into an outer loop (Fig. 7a) , which iteratively decreases f from an upper bound f max to a lower bound f min (Table I) . ...
doi:10.1145/1960397.1960417
dblp:conf/ispd/KnechtelML11
fatcat:wq3h6bdxtza7vizg5rigwjnkni
Assembling 2-D Blocks Into 3-D Chips
2012
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In part, this is due to the wide availability of trustworthy intellectual property (IP) blocks developed for 2D ICs and proven through repeated use. ...
Block-based design reuse is imperative for heterogeneous 3D ICs where memory, logic, analog and micro-electro-mechanical systems (MEMS) dies are manufactured at different technology nodes and circuit modules ...
Therefore, we wrap our methodology into an outer loop (Fig. 7a) , which iteratively decreases f from an upper bound f max to a lower bound f min (Table I) . ...
doi:10.1109/tcad.2011.2174640
fatcat:ctfcfojdqzeavlof6qqixsylfi
An area-optimality study of floorplanning
2004
Proceedings of the 2004 international symposium on Physical design - ISPD '04
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A novel algorithm for rectangular floorplanning with guaranteed 100% area utilization is used to construct new sets of floorplanning benchmarks. ...
A mathematical analysis shows that the aspect ratios of the ZDS benchmarks' blocks are uniformly bounded within [1, 3] in most cases. ...
Previous works on this subject ( [23] , [19] ) analyzed the theoretical upper bounds on the total area achieved by slicing floorplans of soft blocks. ...
doi:10.1145/981066.981083
dblp:conf/ispd/CongNRS04
fatcat:dv5mephmkzhwvjgwydejt3wboa
The quarter-state-sequence floorplan representation
2003
IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications
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An exact formula for counting distinct floorplans is given and compared with existing bounds. A linear time transformation of one Q sequence to another is defined. ...
A floorplan of a bounding box is its dissection into rectangles (rooms) by horizontal and vertical segments. ...
ACKNOWLEDGMENT The authors are grateful to Associate Professor A. Takahashi, Tokyo Institute of Technology for his valuable advice and to Dr. ...
doi:10.1109/tcsi.2003.809442
fatcat:qhd5opqrhvb37gz7d57ss2h4ma
3DIC benefit estimation and implementation guidance from 2DIC implementation
2015
Proceedings of the 52nd Annual Design Automation Conference on - DAC '15
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a priori estimates of 3D power benefits, based on a given design's post-synthesis and 2D implementation parameters. ...
Quantification of three-dimensional integrated circuit (3DIC) benefits over corresponding 2DIC implementation for arbitrary designs remains a critical open problem, largely due to nonexistence of any " ...
Alex Zelikovsky of Georgia State University for discussions leading to the bound of Lemma 1. We also thank Prof. ...
doi:10.1145/2744769.2747954
dblp:conf/dac/ChanNKDS15
fatcat:5u7m5jdghre4bnzakcsk3k6amu
MIDAS: Model for IP-inclusive DFM assessment of system manufacturability
2014
2014 5th European Workshop on CMOS Variability (VARI)
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We present MIDAS: a scalable, IP-inclusive model to predict system manufacturability. ...
The ever increasing demand for quick time-to-market has led to the widespread use of Intellectual Property (IP) in ASIC design methodologies. ...
Thanks also to our foundry partner for making the design kits and DRC/DFM/LVS rule decks available for this work. ...
doi:10.1109/vari.2014.6957079
fatcat:lt5nld7g5vfdtmmigbhg3boc4q
Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis
2010
2010 International Conference on Reconfigurable Computing and FPGAs
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The proposed heuristic methodology integrates fast algorithms based on the B*-tree representation for floorplanning, on bipartite matching for the routers assignment step, and on multicommodity flow for ...
We propose a new custom Network-on-Chip (NoC) topology synthesis methodology consisting of floorplanning, routers assignment, and routing paths calculation steps. ...
Routers Assignment and Links Construction In the second step, IP/cores to routers assignment is done for each floorplan from the list of best M floorplans. ...
doi:10.1109/reconfig.2010.27
dblp:conf/reconfig/Ababei10
fatcat:i32nfygkr5goxhjtjfd4ddv3ay
Retiming for Wire Pipelining in System-On-Chip
2004
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This problem is different from that on a gate-level netlist and is formulated as a wire-retiming problem. Theoretical treatment and a polynomial time algorithm are presented in the paper. ...
Behaviorally, it means that both computation and communication are rescheduled for parallelism. ...
THEORETICAL RESULTS
A. ...
doi:10.1109/tcad.2004.833615
fatcat:osk55nzgxfevdndrv6mockhe44
Floorplanning With Wire Pipelining in Adaptive Communication Channels
2006
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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They built a SoC floorplanner based on the use of adaptive and nonadaptive WP, which optimizes the data rate, taking block delay into account. ...
Index Terms-Floorplanning, systems-on-chip, wire pipelining (WP). ...
CONCLUSION In this paper, we focused on the floorplan of systems-on-chip based on the use of IP blocks and WP interconnects to improve the DR. ...
doi:10.1109/tcad.2006.882590
fatcat:otalc45wxvcztihe5fh336mmi4
Retiming for wire pipelining in System-On-Chip
2003
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)
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This problem is different from that on a gate-level netlist and is formulated as a wire-retiming problem. Theoretical treatment and a polynomial time algorithm are presented in the paper. ...
Behaviorally, it means that both computation and communication are rescheduled for parallelism. ...
THEORETICAL RESULTS
A. ...
doi:10.1109/iccad.2003.159692
fatcat:yb2kpkvfezetlkdz53iu7ucoum
Linear-programming-based techniques for synthesis of network-on-chip architectures
2006
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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We present mixed integer linear programming formulations for the two stages. We also present a clustering based heuristic technique for the second stage to reduce the run times of the formulation. ...
This paper presents novel linear programming based techniques for synthesis of custom NoC architectures. ...
[49] presented a branch and bound technique to map IPs onto a regular mesh based NoC architecture. ...
doi:10.1109/tvlsi.2006.871762
fatcat:fexolmsg6jhcpnvlacwahobaxe
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