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A test methodology for interconnect structures of LUT-based FPGAs

H. Michinishi, T. Yokohira, T. Okamoto, T. Inoue, H. Fujiwara
<i title="IEEE Comput. Soc. Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/tquv56q3mbb3zbshmluyl4dp7a" style="color: black;">Proceedings of the Fifth Asian Test Symposium (ATS&#39;96)</a> </i> &nbsp;
In this papel; we consider testing for programmable interconnect structures of look-up table based FPGAs.  ...  The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them.  ...  Testing for other components, how proposed there. In this paper, we present testing for programmable interconnect structures in the FPGAs with sequential loading.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ats.1996.555139">doi:10.1109/ats.1996.555139</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ats/MichinishiYOIF96.html">dblp:conf/ats/MichinishiYOIF96</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/n5t63sazfjhbjasfhu3rjdmwuy">fatcat:n5t63sazfjhbjasfhu3rjdmwuy</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20171112143555/https://core.ac.uk/download/pdf/12525180.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/14/13/1413b20386bb67fb98378eeadb1ded269afe18b9.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ats.1996.555139"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration

<span title="2020-10-10">2020</span> <i title="Blue Eyes Intelligence Engineering and Sciences Engineering and Sciences Publication - BEIESP"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cj3bm7tgcffurfop7xzswxuks4" style="color: black;">VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE</a> </i> &nbsp;
This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA).  ...  The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs.  ...  Broadly two types of FPGA"s exist based on their programmable nature; a onetime programmable Antifuse FPGA and the unlimited programmable SRAM-based FPGA [2] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.35940/ijitee.l7985.1091220">doi:10.35940/ijitee.l7985.1091220</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ja6lhd5r3bgeziocl55wdqnvim">fatcat:ja6lhd5r3bgeziocl55wdqnvim</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20201009044003/http://www.ijitee.org/wp-content/uploads/papers/v9i12/L79851091220.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.35940/ijitee.l7985.1091220"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology

Vinod Pangracious, Habib Mehrez, Zied Marakchi
<span title="">2013</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5qijqusmybfgrocwnjonoyc7uq" style="color: black;">2013 IEEE International 3D Systems Integration Conference (3DIC)</a> </i> &nbsp;
We have introduced a horizontally partitioned 3-dimensional (3D) design methodology to optimize the BFT based programmable interconnect delay of the Tree-based FPGA.  ...  programmable interconnect topology based 3D Tree-based FPGA improves speed by 2.06 times and reduce interconnect area by 2.8 times compared to 3D Mesh-based FPGA with identical logic resources.  ...  Figure 9 present the TSV assignment of tier 0 and 1 dies of a cluster in the 3D stacked Tree-based FPGA test chip. In our 3D Tree-based FPGA test chip, we have 7 Tree levels with arity set to 4.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/3dic.2013.6702342">doi:10.1109/3dic.2013.6702342</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/3dic/PangraciousMM13.html">dblp:conf/3dic/PangraciousMM13</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xi5agpwiobhtjanqbmqaimixii">fatcat:xi5agpwiobhtjanqbmqaimixii</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180724035131/https://hal.archives-ouvertes.fr/file/index/docid/944767/filename/PID2868325.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/c3/e1/c3e1bb0a71f0b895dfb74b339b16421643e9d012.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/3dic.2013.6702342"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Detection and Diagnosis of Faults in the Routing Resources of a SRAM based FPGAs

Jamuna. S, V. K. Agrawal
<span title="2012-09-25">2012</span> <i title="Foundation of Computer Science"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/b637noqf3vhmhjevdfk3h5pdsu" style="color: black;">International Journal of Computer Applications</a> </i> &nbsp;
The rate of occurrence of permanent faults can be quite high in emerging technologies, and hence there is a need for periodic testing of such FPGAs.  ...  Here, we present an approach for testing FPGA interconnect that exploits the reprogramability of an FPGA to create builtin self test (BIST) logic by configuring it only during off-line testing.  ...  General SRAM based FPGA interconnect structure Figure1 shows a detailed structure of interconnect. It has basically connection block and the switch block (switch matrix).  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5120/8481-2421">doi:10.5120/8481-2421</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/h6xlb6ejqjdjxiv4twe5zvkuoi">fatcat:h6xlb6ejqjdjxiv4twe5zvkuoi</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180721044346/https://research.ijcaonline.org/volume53/number13/pxc3882421.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/9f/67/9f67ab989973adac78331314b3e9610fdf381152.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5120/8481-2421"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time

F.-J. Veredas, M. Scheppler, H.-J. Pfleiderer
<span title="">2006</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qjrrvry5ubgdlarkymvlxuip6m" style="color: black;">Proceedings of the Design Automation &amp; Test in Europe Conference</a> </i> &nbsp;
In this paper, we present a conversion flow for a Look-up Table-based (LUT-based) MPGA without applying re-synthesis but preserving the gate-level netlist and reusing the placement.  ...  LUT-based Programmable Architectures There are two major players in the FPGA market: Xilinx Inc. and Altera Inc.  ...  Zelix MPGA array Current LUT-based MPGAs use a random interconnect structure (e.g. Altera HardCopy-II [3] ).  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2006.243745">doi:10.1109/date.2006.243745</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/date/VeredasSP06.html">dblp:conf/date/VeredasSP06</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/iugzmwnv4zex3lfcoe2blums6y">fatcat:iugzmwnv4zex3lfcoe2blums6y</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170922011115/https://www.date-conference.com/proceedings-archive/PAPERS/2006/DATE06/DF_FILES/05D_1.PDF" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/aa/c0/aac095d1f0a0bd22318a33b8d058498a59f66c57.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2006.243745"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Fault Testing and Diagnosis of Sram based FBGA using Built-In-Self-Test-Architecture

Nagma. P, Ramachandran. S, Sathishkumar. E
<span title="2018-02-28">2018</span> <i title="South Asia Management Association"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/oarwpnpqjjfbbkyptszxdp4ch4" style="color: black;">International Journal of Trend in Scientific Research and Development</a> </i> &nbsp;
) based field-programmable gate arrays (FPGAs). can test both the interconnect resources [wire channels and programmable switches (PSs)] and lookup tables (LUTs) in the configurable logic blocks (CLBs)  ...  Built in Self-Test (BIST) is a design technique that allows a circuit to test itself .The proposed method of a built-in self-test (BIST) design for fault detection and fault diagnosis of static-RAM (SRAM  ...  FAULT MODELS Design a BIST structure for both CLB and interconnect resource testing in SRAM-based FPGAs.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.31142/ijtsrd9415">doi:10.31142/ijtsrd9415</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/wtdhleviqjaj5if7pgdynwcire">fatcat:wtdhleviqjaj5if7pgdynwcire</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200307170336/https://www.ijtsrd.com/papers/ijtsrd9415.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/03/e6/03e6ab248545fcc1ff9afe9b7a26c0bbee546812.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.31142/ijtsrd9415"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Architecture level optimization of 3-dimensional tree-based FPGA

Vinod Pangracious, Emna Amouri, Zied Marakchi, Habib Mehrez
<span title="">2014</span> <i title="Elsevier BV"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/j4boqfodxvd6baghfcgla24jdy" style="color: black;">Microelectronics Journal</a> </i> &nbsp;
We describe a methodology to design and optimize Three-dimensional (3D) Tree-based FPGA by introducing a break-point at particular tree level interconnect to optimize the speed, area, and power consumption  ...  The ability of the design flow to decide a horizontal or vertical network break-point based on design specifications is a defining feature of our design methodology.  ...  Section 6 presents the impact of LUT and cluster size of Tree-based FPGA architecture on performance. Section 7 explains power optimization methodology of 3D Tree-based FPGA.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/j.mejo.2013.12.011">doi:10.1016/j.mejo.2013.12.011</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/sxyjcy3cwnd57kainxzd3txdc4">fatcat:sxyjcy3cwnd57kainxzd3txdc4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180725134819/https://hal.archives-ouvertes.fr/hal-00944759/document" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/ba/55/ba55d374e25c6de729d344ff2bf591f09a9de174.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/j.mejo.2013.12.011"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> elsevier.com </button> </a>

A Methodology for FPGA to Structured-ASIC Synthesis and Verification

M. Hutton, R. Yuan, J. Schleicher, G. Baeckler, S. Cheung, Kar Keng Chua, Hee Kong Phoon
<span title="">2006</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qjrrvry5ubgdlarkymvlxuip6m" style="color: black;">Proceedings of the Design Automation &amp; Test in Europe Conference</a> </i> &nbsp;
The most important aspects of this methodology are the use of physically identical blocks for difficult-to-verify PLLs, I/O and RAM and a structured re-synthesis of FPGA logic blocks to target cells that  ...  Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based  ...  A structured ASIC consists of a base array of hard blocks (e.g.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2006.243775">doi:10.1109/date.2006.243775</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/date/HuttonYSBCCP06.html">dblp:conf/date/HuttonYSBCCP06</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ydacdxgdhzbfhct2lkur2gnvme">fatcat:ydacdxgdhzbfhct2lkur2gnvme</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20071130115746/http://www.date-conference.com/conference/proceedings/PAPERS/2006/DATE06/DF_FILES/05D_6.PDF" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/f0/3a/f03a0a1230aa31efe5fa6ea3d524748675c54e54.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2006.243775"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System

Pavel Kubalik, Jiri Kvasnicka, Hana Kubatova
<span title="">2007</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/6zmpupdvf5fhhnjefe33o3wvm4" style="color: black;">2007 IEEE Design and Diagnostics of Electronic Circuits and Systems</a> </i> &nbsp;
Two FPGAs are used for duplex system design, each including the combination of totally self-checking blocks based on parity predictors to obtain better dependability parameters.  ...  The implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented.  ...  We will focus on the fault list creation, which would make shorts and opens testing possible, either based on the fault injection into the interconnection of the FPGA (the risk test set) or based on the  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ddecs.2007.4295312">doi:10.1109/ddecs.2007.4295312</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ddecs/KubalikKK07.html">dblp:conf/ddecs/KubalikKK07</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/e77y3mssbrhkvihfxydwmfozbq">fatcat:e77y3mssbrhkvihfxydwmfozbq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170811191651/http://ddd.fit.cvut.cz/publ/2007/Kubalik_DDECS.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/37/39/37399cdfb4d3ca3f45410dd95e4119cd03590573.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ddecs.2007.4295312"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Cellular Automata-Based Reconfigurable Systems as Transitional Approach to Gigascale Electronic Architectures

James C. Lyke, Greg W. Donohoe, Shashi P. Karna
<span title="">2002</span> <i title="American Institute of Aeronautics and Astronautics (AIAA)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/rq5e3ewv7bgrnf57ibetvdgysa" style="color: black;">Journal of Spacecraft and Rockets</a> </i> &nbsp;
If the LUTs are imple- mented as memory cells in a shift register, it is possible to program Inputs Out Fig. 1 CA FPGA based on a tesselation of LUTs.  ...  The plies may be individually tested and even used as a decallike MCM for a variety of applications. Simple MCMs have been built using this technique (Fig. 6), resulting in a 100-j2m structure.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.2514/2.3860">doi:10.2514/2.3860</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/be7njqryg5eyzi5mkylhngdzle">fatcat:be7njqryg5eyzi5mkylhngdzle</a> </span>
<a target="_blank" rel="noopener" href="https://archive.org/details/sim_journal-of-spacecraft-and-rockets_july-august-2002_39_4/page/489" title="read fulltext microfilm" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Archive [Microfilm] <div class="menu fulltext-thumbnail"> <img src="https://archive.org/serve/sim_journal-of-spacecraft-and-rockets_july-august-2002_39_4/__ia_thumb.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.2514/2.3860"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA)

Vinod Pangracious, Habib Mehrez, Umer Farooq, Zied Marrakchi
<span title="">2013</span> <i title="ACM Press"> Proceedings of the 10th FPGAworld Conference on - FPGAworld &#39;13 </i> &nbsp;
We describe the design and exploration methodology to optimize 3-dimensional (3D) Heterogeneous Tree-based FPGAs (HT-FPGAs) by introducing a break-point at a particular tree level interconnect to optimize  ...  The ability of the flow to decide a horizontal or vertical partitioning of the programmable tree network based on design specifications is a defining feature.  ...  The vertically partitioned test chip with 7 Tree levels and 16K LUTs require 20480 TSVs for a fully connected (Rent=1) 2 tier 3D HT-FPGA.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/2513683.2513686">doi:10.1145/2513683.2513686</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/w5r6eqay6bdnle6mlxx4ba6arm">fatcat:w5r6eqay6bdnle6mlxx4ba6arm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170925093609/https://hal.archives-ouvertes.fr/hal-00873151/document" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/43/b8/43b862546faacaa490b405fe34c41da9314b4782.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/2513683.2513686"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

FPGA architectural research: a survey

S. Brown
<span title="">1996</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/hkpx3vsnhrfb7jh6hlwads7olq" style="color: black;">IEEE Design &amp; Test of Computers</a> </i> &nbsp;
For practical reasons, these studies assumed a logic block to be a lookup table (LUT) memory and defined logic-block complexity as simply the number of inputs K to the LUT.  ...  The first FPGA architecture studies reported in research publications concerned the complexity of an FPGA's logic b l o~k .~,~ The basic idea was to study how much circuitry a single logic block should  ...  We show a set of curves for hardwired logic blocks based on 2to 7-input LUTs.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/54.544531">doi:10.1109/54.544531</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/fdmniociirdz5aavt2m4bdibju">fatcat:fdmniociirdz5aavt2m4bdibju</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170829013956/http://arantxa.ii.uam.es/~die/%5BLectura%20FPGA%20Architecture%5D%20FPGA%20architectural%20research.%20A%20survey.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/a9/98/a998c6dc959985a97c7813f455db24f8dc2719ee.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/54.544531"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Reconfigurable Artificial Neural Networks

Abhirup Basu, Pinaki Bisaws, Sarmi Ghosh, Debarshi Datta
<span title="2017-12-15">2017</span> <i title="Foundation of Computer Science"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/b637noqf3vhmhjevdfk3h5pdsu" style="color: black;">International Journal of Computer Applications</a> </i> &nbsp;
To improve the speed of the system a LUT based activation function is implemented as a ROM which contains neuron synaptic weights and thus stores the inner product.  ...  Implemented ANN on Field Programmable Gate Array (FPGA) can be used for a variety of real life applications.  ...  In this paper, a modified ANN structure is described in VHDL and then it implemented on FPGA. The computation speed can be improved by using LUT based nonlinear function in the activation block.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5120/ijca2017915961">doi:10.5120/ijca2017915961</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/adah5geoejccplxzwod7qjxhyu">fatcat:adah5geoejccplxzwod7qjxhyu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180602174607/https://www.ijcaonline.org/archives/volume179/number6/basu-2017-ijca-915961.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/a1/be/a1be18aae07cf0ac579bb324dc3fdf934ed718dc.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5120/ijca2017915961"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Methodology for high level estimation of FPGA power consumption

Vijay Degalahal, Tim Tuan
<span title="">2005</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fkjmyf3l45eo5ovjdnpeqpdjd4" style="color: black;">Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC &#39;05</a> </i> &nbsp;
In this work, we leverage the FPGA architecture to present an efficient and accurate methodology for pre-silicon dynamic power estimation of FPGA-based designs.  ...  We apply the methodology to estimate the power consumption of a state-of-the-art Spartan-3 TM FPGA family, evaluate the estimation results against silicon measurements, and present a detailed power breakdown  ...  In our work, we leverage the FPGA architectural details to determine the interconnect capacitance and provide for a methodology to capture the pre layout capacitance.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1120725.1120986">doi:10.1145/1120725.1120986</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/aspdac/DegalahalT05.html">dblp:conf/aspdac/DegalahalT05</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/gtxwr7rwwfcojig7kopmvk4m4e">fatcat:gtxwr7rwwfcojig7kopmvk4m4e</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20060908004534/http://www.cse.psu.edu/~degalaha/paper/final.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/4e/8a/4e8a464f8f1be8c22231dc0790677396318a18a1.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1120725.1120986"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

TeMNOT: A test methodology for the non-intrusive online testing of FPGA with hardwired network on chip

Muhammad Aqeel Wahlah, Kees Goossens
<span title="">2013</span> <i title="Elsevier BV"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/brvj2ugukfgvhevdy5lwzvdy6m" style="color: black;">Microprocessors and microsystems</a> </i> &nbsp;
Functional test verifies FPGA architecture for the intended set of applications [8] , whereas structural test verifies FPGA architecture irrespective of the intended set of applications [10].  ...  Importantly, the proposed test methodology exhibits a non-intrusive behaviour that means it does not affect the applications and FPGA regions, which are not being tested, in terms of configuration, programming  ...  The nature of the test is structural, which ensures a high percentage of fault detection for the target FPGA architecture.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/j.micpro.2012.05.011">doi:10.1016/j.micpro.2012.05.011</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ylk5pip42vfjdgdegcu7myhi3a">fatcat:ylk5pip42vfjdgdegcu7myhi3a</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170810233557/http://www.es.ele.tue.nl/~kgoossens/2013-micpro.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/20/0a/200a2c08471b1cd1377041fbedc2f753266b8742.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/j.micpro.2012.05.011"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> elsevier.com </button> </a>
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