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A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology
2021
North atlantic university union: International Journal of Circuits, Systems and Signal Processing
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The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). ...
The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. ...
A Low Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC was implemented. ...
doi:10.46300/9106.2021.15.62
fatcat:6ppqbmc24jb4lcn4pcxt54jkxm
2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26
2018
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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., see 2723-2736
, VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems; TVLSI Feb. 2018 262-271 Hsieh, Y., see Tsai, Y., TVLSI May 2018 945-957 ...
., +, TVLSI Oct. 2018 2050-2060 A High-Speed 2-bit/Cycle SAR ADC With Time-Domain Quantization. Qiu, L., +, TVLSI Oct. 2018 2175-2179 A Hybrid Design Automation Tool for SAR ADCs in IoT. ...
., +, TVLSI April 2018 756-767
A High-Speed 2-bit/Cycle SAR ADC With Time-Domain Quantization.
Qiu, L., +, TVLSI Oct. 2018 2175-2179
A Hybrid Design Automation Tool for SAR ADCs in IoT. ...
doi:10.1109/tvlsi.2019.2892312
fatcat:rxiz5duc6jhdzjo4ybcxdajtbq
Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs
2021
IEEE Open Journal of Solid-State Circuits
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Furthermore, this paper presents a review and addresses the benefits of those hybrid architectures. ...
register, SAR. ...
Fig. 12 illustrates a systematic block diagram of [17] . The N-path TI structure up-modulates the NTF to the IF frequency. ...
doi:10.1109/ojsscs.2021.3118668
fatcat:s5mn2rqw2fdghfnms7dphrvvtq
A Mismatch Calibration Technique for SAR ADCs Based on Deterministic Self-Calibration and Stochastic Quantization
2020
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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A capacitive DAC is an important building block of a charge-redistribution SAR ADC, for its size has a significant impact on performance. ...
This approach is experimentally validated on a prototype 10-bit SAR ADC fabricated in TSMC 28-nm LP CMOS technology, demonstrating an INL and SFDR improvement of respectively 6.4 LSB and 14.9 dB at 85 ...
(b) Inter-digitized layout structure of the split-capacitor array.
Fig. 13 . 13 (a) SAR logic. (b) Asynchronous clock generator of the SAR control logic. ...
doi:10.1109/tcsi.2020.2985816
fatcat:o57m4mvndzgg5nfs6iiu2l44mi
Event-Driven ECG Sensor in Healthcare Devices for Data Transfer Optimization
2020
Arabian Journal for Science and Engineering
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The modeled LC-ADC guarantees a signal quality in terms of PRD comparable to the PRD of the SAR ADC with DWT compression. ...
That is better than the 71.87% BCR of the 12-bit 1-kHz SAR ADC with DWT compression. ...
to reduce
SAR ADC output
data length
Asynchronous
dynamic logic and
flexible resolution
SAR ADC
-
SAR ADC with two
sampling
frequencies and
data compression
Dynamic tracking
SAR ADC ...
doi:10.1007/s13369-020-04483-w
pmid:32421087
pmcid:PMC7223297
fatcat:wc7lzdmyprcgvax6gs66efebya
2020 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 67
2020
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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., +, TCSI Jan. 2020 198-211
A Novel Asynchronous CA Neuron Model: Design of Neuron-Like Non-
linear Responses Based on Novel Bifurcation Theory of Asynchronous
Sequential Logic Circuit. ...
Novel Asynchronous CA Neuron Model: Design of Neuron-Like Nonlinear Responses Based on Novel Bifurcation Theory of Asynchronous Sequential Logic Circuit. ...
An N-Path Filter Design Methodology With Harmonic Rejection, Power Reduction, Foldback Elimination, and Spectrum Shaping. ...
doi:10.1109/tcsi.2021.3055003
fatcat:kbmst5td2bbvtl7vpbj3knnkri
The SALT—Readout ASIC for Silicon Strip Sensors of Upstream Tracker in the Upgraded LHCb Experiment
2021
Sensors
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A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented. ...
It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed ...
The founders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results. ...
doi:10.3390/s22010107
pmid:35009648
pmcid:PMC8747391
fatcat:adhcsr3f5zfjxemumhujdys26i
2019 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 66
2019
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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., +, TCSI Feb. 2019 513-523
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With
Optimal Code Transfer Technique. ...
., +, TCSI Aug. 2019 2817-2830 Design of a 0.20-0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications. ...
Analysis of SRAM Enhancements Through Sense Amplifier ...
doi:10.1109/tcsi.2020.2966967
fatcat:f663jj5g45e3peggn3gwn5jys4
Hardware Efficient Solutions for Wireless Air Pollution Sensors Dedicated to Dense Urban Areas
2020
Remote Sensing
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This algorithm allows for the reduction of the noise amplitude by 23 dB and enables a reduction of the number of wireless communication sessions with a base station (BS) by 70%–80%. ...
A possibility of the implementation of a relatively dense network of wireless air pollution sensors that can collect and process data in real time was the motive behind our research and investigations. ...
A prototype ADC of this type, developed by us, is based on the successive approximation register (SAR) architecture. ...
doi:10.3390/rs12050776
fatcat:yipkgbxlcjgyxjofukqmnhu6em
2018 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 65
2018
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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., +, TCSI June 2018 1994-2004
Asynchronous circuits
A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR
ADC. ...
., +, TCSI March 2018 870-880
A Systematic Design Method for Direct Delta-Sigma Receivers. ...
doi:10.1109/tcsi.2019.2896877
fatcat:3lzpngw2ofdjhiculf7ehrjeam
Integrated Circuits and Electrode Interfaces for Noninvasive Physiological Monitoring
2014
IEEE Transactions on Biomedical Engineering
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A systematic approach to instrumentation amplifier (IA) design using CMOS transistors operating in weak inversion is shown to offer high energy and noise efficiency. ...
Practical methodologies to obviate 1/f noise, counteract electrode offset drift, improve common-mode rejection ratio, and obtain subhertz high-pass cutoff are illustrated with a survey of the state-of-theart ...
Fukuoka for analysis of indirectly measured ECG and EMG signals, and T. Kerth for contributions to design of and experiments with the Cognionics 64-channel wireless dry EEG headset. ...
doi:10.1109/tbme.2014.2308552
pmid:24759282
fatcat:wy75uz2hhvasvhm3mkcvguwhc4
Evolvable Smartphone-Based Point-Of-Care Systems For In-Vitro Diagnostics
2016
Zenodo
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Among possible implementation strategies, platform-based design stands as a particularly suitable entry point. ...
advent of a preventive and personalized medicine. ...
Several methodologies, including Cardin's, thus propose a systematic approach to design for flexibility and may constitute the basis of a formal approach to design for evolvability. ...
doi:10.5281/zenodo.204579
fatcat:okesojvyjjghpntsmb676lvsh4
SAR ADCs Design and Calibration in Nano-scaled Technologies
2018
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An analytical model is proposed to estimate the resolution and predict the yield of LU-SAR ADCs with presence of comparator offset mismatch. A background calibration technique [...] ...
Loop-unrolled (LU) SAR ADCs have been recognized as a promising architecture for high-speed applications. ...
Asynchronous SAR ADC and design challenges
Loop-unrolled SAR ADC To enhance the sampling rate of SAR ADCs, both the architecture and timing control have been thoroughly explored, aiming to overcome the ...
doi:10.1184/r1/6721385.v1
fatcat:urcvemsywvf5hn7qtoe32orahm
First report of long term measurements of the MGGL laboratory in the Mátra mountain range
2017
Classical and quantum gravity
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Here we report RUN-0 data, that prepares systematic and synchronized data collection of the next run period. ...
In this paper we describe the research potential of the MGGL, list the installed equipments and summarize the experimental results of RUN-0. ...
Acknowledgement The contribution and support of Nitrokemia Zrt. in particular Á. Váradi and V. Rofrits is acknowledged. We also thank the construction work of Geofaber Zrt. ...
doi:10.1088/1361-6382/aa69e3
fatcat:3muynqanprfyhcifbdjyuvmqkm
Feasibility of future epidemiological studies on possible health effects of mobile phone base stations
2007
Bioelectromagnetics
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We also use a 3 µm X 3 µm membrane planar patch model with a Smoluchowski equation-based model to investigate local electroporation behavior due to pulses of a wide range of durations and amplitudes. ...
The small, residual pores have lifetimes of order seconds, which is a mechanism for translating submicrosecond interactions to the physiological time scale of 0.1 ms to seconds. ...
using these methodologies, including experimental design and sample preparation • The application of these tools to a wide-variety of biological problems, including large-scale analysis of protein expression ...
doi:10.1002/bem.20298
pmid:17080459
fatcat:l23qxeq7cnh2xiz7yvfywdz5i4
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