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D&T Conferences

1986 IEEE Design & Test of Computers  
distributed systems Database machines PLA design and test Reliable VLSI design Image and signal processing Cross-disciplinary sessions: Intel 80386 system design MicroVAX chip set AT&T microsystem  ...  With a goal of high fault coverage, the processor is tested using a variety of techniques such as built-in self-test and special testability hooks.  ... 
doi:10.1109/mdt.1986.295003 fatcat:q36icdko3rcivdieaaoacmvup4

Manufacturability of Mixed Signal Systems

Manuel d'Arbreu, Abhijit Chatterjee
1999 International Conference on VLSI Design  
This level of integration has resulted in a need for CAD systems for software, as well as hardware, synthesis.  ...  The advent of deep submicron processing technology has made it possible and desirable to integrate one or more processor cores, program ROM/RAM, and application-specific circuitry all on a single IC.  ...  A CAD framework for embedded system design requires many different tools including software compilers, assemblers, and instruction-level simulators, and HDL compilers and simulators.  ... 
dblp:conf/vlsid/dArbreuC99 fatcat:xlyezx74dzadrkxsyozwxawh5m

Design and Analysis of 32-bit Parallel Prefix Adders for Low Power VLSI Applications

Samraj Daphni, Kasinadar Sundari Vijula Grace
2019 Advances in Science, Technology and Engineering Systems  
To minimize the Power Delay Product (PDP) of Digital Signal Processing (DSP) processors is necessary for high performance in Very Large Scale Integration (VLSI) applications.  ...  In this paper, a 32-bit various Parallel Prefix adders design is proposed and compared the performance results on the aspects of area, delay and power.  ...  The adder performance which is used in the device is only measured the high speed and accuracy of a processor or system.  ... 
doi:10.25046/aj040213 fatcat:mwbot4rn5zautb3uz4xaonboxq

VHDL Implementation of GCD Processor with Built in Self Test Feature

Rekha Devi, Jaget Singh, Mandeep Singh
2011 International Journal of Computer Applications  
In this paper we have design GCD (greatest common divider) processors in VHDL with BIST capability and compared the area overhead of with and without BIST.  ...  The Very Large Scale Integration (VLSI) has a dramatic impact on the growth of digital technology. VLSI has not only reduced the size and the cost, but also increased the complexity of the circuits.  ...  Simulation results of GCD processor with BIST Application The figure 7 shows the simulation results of GCD processor with BIST, having two signals when Test signal is high BIST section is activated,  ... 
doi:10.5120/3000-4034 fatcat:k5sw2sftdrhlvjchgtjnid57ti

Parallel logic simulation of VLSI systems

Roger D. Chamberlain
1995 Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95  
However, with continuing increases in the capabilities of VLSI systems, the simulation task has become a significant bottleneck in the design process.  ...  As a result, researchers are attempting to exploit parallel processing techniques to improve the performance of VLSI logic simulation.  ...  ACKNOWLEDGMENT The author would like to thank Mary Bailey for her insightful comments on an early draft of this manuscript.  ... 
doi:10.1145/217474.217520 dblp:conf/dac/Chamberlain95 fatcat:r7pbllgnnzaytedlvbd6blno4m

Parallel Logic Simulation of VLSI Systems

Roger D. Chamberlain
1995 Proceedings - Design Automation Conference  
However, with continuing increases in the capabilities of VLSI systems, the simulation task has become a significant bottleneck in the design process.  ...  As a result, researchers are attempting to exploit parallel processing techniques to improve the performance of VLSI logic simulation.  ...  ACKNOWLEDGMENT The author would like to thank Mary Bailey for her insightful comments on an early draft of this manuscript.  ... 
doi:10.1109/dac.1995.250078 fatcat:6z2noirad5gllocr7vab4yokqu

A parallel computer architecture for continuous simulation

J.O. Hamblen, C.O. Alford
1988 IEEE Transactions on Aerospace and Electronic Systems  
Tan, and other numerous students, in the design and construction of the prototype machine.  ...  For high performnce, a high speed adder and hardware multiplier are required. The fixed point processor performs two operand fetches, a multiply, a double precision addition, and a store in 250 ns.  ...  Additional work is needed in the development of VLSI chips designed to support parallel architectures, the development of parallel compilers for continuous system simulation languages, and new integration  ... 
doi:10.1109/7.18639 fatcat:mrf2u3pcjzdpzpog5jwt3svckq

Implementation of FPGA Based Fault Injection Tool (FITO) for Testing Fault Tolerant Designs

Swathi Rudrakshi, Vasujadevi Midasala, S. Naga Kishore Bhavanam
2012 International Journal of Engineering and Technology  
Modelsim Xilinx Edition (MXE) will be used for functional simulation and Xilinx ISE tools will be used for synthesis and performance analysis.  ...  In current VLSI technology fault injection has become a popular technique for experimentally verifying the fault tolerant based designs.  ...  Y, Naga Supraja help in the Implementation of FPGA Based Fault Injection Tool (FITO) For Testing Fault Tolerant Design.  ... 
doi:10.7763/ijet.2012.v4.424 fatcat:iyrqgludqfa63ewsxpehvnnd7a

Verification of Systems-on-Chip Designs

Rahul Razdan, Apurva Kalia, Manu Lauria
1999 International Conference on VLSI Design  
Advances in semiconductor technologies, and the aggressive time-to-market, performance, and cost requirements have led to a paradigm shift in electronic system design, with the evolution of system-level-integration  ...  and ADC/DAC cores, high-speed custom-designed blocks, as well as asynchronous interfaces.  ...  VLSI Signal Processing in FPGAs Sudip Nag and H. K.  ... 
dblp:conf/vlsid/RazdanKL99 fatcat:djpivu2percalaab2f3r5yj6he

Implementation of 32 Bit RISC Processor using Reversible Gates

Jyoti Choudhary, Mahesh Kumar Sharma
2019 Zenodo  
The aim of this project is to design the schematic and simulation for a 32 bit RISC processor using reversible logic peres gate.  ...  Design is implemented and verified in VHDL in Xilinx 14.3.  ...  The CMOS logic for the above design can be implemented, synthesized and simulated using VLSI software tools like Tanner Tools software.  ... 
doi:10.5281/zenodo.3591488 fatcat:zxz43vurz5fxfarnuysvy2ubjy

An Adaptive Pipeline Processor For Real-Time Image Processing

Neil Storey, Richard C. Staunton, Michael J. W. Chen
1990 Automated Inspection and High-Speed Vision Architectures III  
Each identical processor element (PE) can be programmed by a separate controller over a high speed communications channel, and can perform a range of operations including filtering, averaging, edge-detection  ...  A typical image processing arrangement would consist of a series of identical PEs connected in series and a separate control computer which is responsible for configuring the system.  ...  If a high level processor is used, the pipeline can be considered to be a pre-processor that performs low level functions and effectively reduces the data bandwidth for the high level system.  ... 
doi:10.1117/12.969953 fatcat:npmd3wnndned7bujptjrifm2rq

A sub-100-milliwatt dual-core HOG accelerator VLSI for real-time multiple object detection

Kenta Takagi, Kosuke Mizuno, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013 2013 IEEE International Conference on Acoustics, Speech and Signal Processing  
The performance of this accelerator is demonstrated on a pedestrian detection system.  ...  The processor employs three techniques: a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification, a dual core architecture for parallel feature extraction,  ...  ACKNOWLEDGMENTS The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with STARC, e-Shuttle  ... 
doi:10.1109/icassp.2013.6638112 dblp:conf/icassp/TakagiMIKY13 fatcat:vd56qmxe3zapbk2nnl3qbclni4

Implementation of AMBAASB Memory Controller with Power Analysis

Vipin Kumar
2015 International Journal on Recent and Innovation Trends in Computing and Communication  
AMBA-ASB has several features i.e it provides parallel communication, high clock frequency, high performance system.  ...  The work presented here is a summary of result obtained when AMBA-ASB memory controller was simulated and synthesized, using ModelSim 6.4a and Xilinx ISE 14.7.  ...  The AMBA is designed, tested and licensed by ARM Limited. ARM is embedded processor which is SoC (System on chip).  ... 
doi:10.17762/ijritcc2321-8169.1503115 fatcat:utrqn6nfnfcypg6d3c6v2mxuae

Optical interconnects for neural and reconfigurable VLSI architectures

D. Fey, W. Erhard, M. Gruber, J. Jahns, H. Bartelt, G. Grimm, L. Hoppe, S. Sinzinger
2000 Proceedings of the IEEE  
Furthermore, we designed and manufactured fiber arrays, which will be the core element for a convenient test station for the 2-D optoelectronic I/O interface of OE-VLSI circuits.  ...  For the optical interconnects, a planar-integrated free-space optical system has been designed leading to an optical multichip module.  ...  After arranging the interfaces between optics and electronics, the optical and optoelectronic part of our system were designed separately as well as the fiber array we wanted to use as a test system for  ... 
doi:10.1109/5.867697 fatcat:ibvdc3rgvvfdtn4vrbrr7s6xpu

VLSI-Based System for Predicting Ventricular Arrhythmia

Mayuri M. Salunke
2019 International Journal for Research in Applied Science and Engineering Technology  
It presents the simulated design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for the predicting of ventricular arrhythmia disease using a set of ECG features and a naïve Bayes  ...  The database of the heart signal recordings from the MIT PhysioNet is used as a validation training data set to evaluate the performance of the processor.  ...  In general, the end-to-end system was designed in VLSI, and a testbench for the ECG signal was created to simulate it by modeling the input data.  ... 
doi:10.22214/ijraset.2019.7058 fatcat:ticglfocjfbxbf74bul5ijnwtm
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