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Sublogarithmic deterministic selection on arrays with a reconfigurable optical bus

Yijie Han, Yi Pan, Hong Shen
2002 IEEE transactions on computers  
AbstractÐThe Linear Array with a Reconfigurable Pipelined Bus System (LARPBS) is a newly introduced parallel computational model, where processors are connected by a reconfigurable optical bus.  ...  To our best knowledge, this is the best deterministic selection algorithm on any model with a reconfigurable optical bus.  ...  buses using switches (APPBS) [8] , the array with synchronous optical switches (ASOS) [28] , the reconfigurable array with spanning optical buses (ROSOB) [29] .  ... 
doi:10.1109/tc.2002.1009153 fatcat:msi3h7kunffl3ht5wtam35ysv4

Parallel optical interconnects may reduce the communication bottleneck in symmetric multiprocessors

Jacques Henri Collet, Wissam Hlayhel, Daniel Litaize
2001 Applied Optics  
and a short memory access latency.  ...  We start from a detailed analysis of the communication issues in today's symmetric multiprocessor (SMP) architectures to study the benefits of implementing optical interconnects (OI) in these machines.  ...  Optical Interconnects for a Symmetric Multiprocessor Cache-Coherent Switch The main limitation of shared electric busses comes from the capacitance of connected transceivers that slows down the propagation  ... 
doi:10.1364/ao.40.003371 pmid:18360362 fatcat:f53vxtdnybblxhpl3gulluizha

Pipelined communications in optically interconnected arrays

Zicheng Guo, Rami G. Melhem, Richard W. Hall, Donald M. Chiarulli, Steven P. Levitan
1991 Journal of Parallel and Distributed Computing  
The second is a two-dimensional architecture in which processors are placed in a square grid and interconnected to one another through horizontal and vertical pipelined optical buses.  ...  Further, they permit all processors to have simultaneous access to the buses using slots within a pipelined cycle.  ...  In this paper, we present two multiprocessor architectures, called Array Processors with Pipelined Buses ( APPB ) , which employ optical bus interconnections in processor arrays.  ... 
doi:10.1016/0743-7315(91)90130-2 fatcat:hsevn53zlbaxhmopgp6nlcg2bi

SYMNET: an optical interconnection network for scalable high-performance symmetric multiprocessors

Ahmed Louri, Avinash Karanth Kodi
2003 Applied Optics  
As a solution, we propose a scalable address subnetwork called symmetric multiprocessor network ͑SYMNET͒ in which address requests and snoop responses of SMPs are implemented optically.  ...  SYMNET can scale up to hundreds of processors while still using fast snooping-based cache-coherence protocols, and additional performance gains may be attained with further improvement in optical device  ...  Litaize and J. H. Collet for their comments on this work.  ... 
doi:10.1364/ao.42.003407 pmid:12816328 fatcat:fea2igxnkzetnbdxzb3ltktvwi

Bi-directional optical backplane bus for general purpose multi-processor board-to-board optoelectronic interconnects

S. Natarajan, Chnunhe Zhao, R.T. Chen
1995 Journal of Lightwave Technology  
The backplane bus demonstrated, is for general-purpose and therefore compatible with such IEEE standardized buses as VMEbus, Futurebus and FASTBUS, and can function as a backplane bus in existing computing  ...  The backplane bus reported here employs arrays of multiplexed polymer-based waveguide holograms in conjunction with a waveguiding plate, within which 16 substrate guided waves for 72 (8 x 9) cascaded fanouts  ...  The surface-normal fan-out is provided by a linear hologram array located between the backplane and the processor/memory boards.  ... 
doi:10.1109/50.390219 fatcat:zb53d7yx3vcnff3j7ry2elzhfu

An optical interconnection network and a modified snooping protocol for the design of large-scale symmetric multiprocessors (SMPs)

A. Louri, A.K. Kodi
2004 IEEE Transactions on Parallel and Distributed Systems  
In Symmetric Multiprocessors (SMPs), the cache coherence overhead and the speed of the shared buses limit the address/ snoop bandwidth needed to broadcast transactions to all processors.  ...  As a solution, a scalable address subnetwork called Symmetric Multiprocessor Network (SYMNET) is proposed in which address requests and snoop responses of SMPs are implemented optically.  ...  Litaize for pointing out the limitations of SMPs in a quantitative manner. They would also like to thank Professor J. Collet for many fruitful discussions and suggestions.  ... 
doi:10.1109/tpds.2004.75 fatcat:uor76io2vjbg7ooep4776dgjk4

Architectural approach to the role of optics in monoprocessor and multiprocessor machines

Jacques Henri Collet, Daniel Litaize, Jan Van Campenhout, Chris Jesshope, Marc Desmulliez, Hugo Thienpont, James Goodman, Ahmed Louri
2000 Applied Optics  
The bottlenecks resulting from and the benefits of implementing OI's are discussed with respect to symmetric multiprocessors, rings, and distributed shared-memory supercomputers.  ...  Therefore the higher the connectivity ͑possibly with optics͒, the shorter the path to another node, but the more expensive the network and the more complex the structure of electronic nodes.  ...  This study partly summarizes the conclusions of the Workshop on Optical Communications and Computer Sciences ͑WOCCS͒ that was held in Toulouse, France, in March 1999.  ... 
doi:10.1364/ao.39.000671 pmid:18337941 fatcat:mowm54a6b5bidk3v5epnutx2a4

The application of threshold logic to the design of sequential machines

Gilbert M. Masters, Richard L. Mattson
1966 Annual Symposium on Switching and Automata Theory  
Digital Communication through fading multi-path channels: Characterization of fading multi-path channels, the effect of signal characteristics on the choice of a channel model, frequency-Nonselective,  ...  slowly fading channel, diversity techniques for fading multi-path channels, Digital signal over a frequency-selective, slowly fading channel, coded wave forms for fading channels, multiple antenna systems  ...  Processor and memory organization: Structural unit in as processor, processor selection for an embedded systems.  ... 
doi:10.1109/swat.1966.29 dblp:conf/focs/MastersM66 fatcat:ierxfghv4vcpbbh2iaktwfdzlm

The Blue Gene/Q Compute chip

Ruud Haring
2011 2011 IEEE Hot Chips 23 Symposium (HCS)  
 External IO -PCIe Gen2 interface System-on-a-Chip design : integrates processors, memory and networking logic into a single chip BG/Q Processor Unit  A2 processor core -Mostly same design  ...  and buses ECC protected • Minor buses, GPRs, FPRs: parity protected, with recovery • Stacked / DICE latches Single MPI Task User defined parallelism User defined transaction start User defined  ...  Design Challenges --continued And the enemy is us…  Methodology Complexity -Processor cores originated in a high-speed custom design methodology -Rest of the chip implemented as ASIC  Required merging  ... 
doi:10.1109/hotchips.2011.7477488 fatcat:nhwlkj3x2zfwjngllgct55plta

Star: A Local Network System for Real-Time Management of Imagery Data

Chuan-Lin Wu, Tse-Yun Feng, Min-Chang Lin
1982 IEEE transactions on computers  
A model for comparing cost-effectiveness among Starnet, crossbar, and multiple buses is included.  ...  The objective is to accomplish a cost-effective system which provides multiple users a real-time service of manipulating very large volume imagery information and data.  ...  Synchronous Operation: The synchronous operation of baseline network and crossbar switch are modeled by assuming each input link generate a request with probability Po in every cycle.  ... 
doi:10.1109/tc.1982.1675901 fatcat:bab67cqjnjgmxe5h53d6xwdmpe

The Scalable Coherent Interface and related standards projects

D.B. Gustavson
1992 IEEE Micro  
The SCI protocols support cache coherence in a distributed-shared-memory multiprocessor model, message passing, I/O, and local-area-network-like communication over fiber optic or wire links.  ...  P1596.1 defines the architecture of a bridge between SCI and VME; P1596.2 compatibly extends the cache coherence mechanism for efficient operation with kiloprocessor systems; P1596.3 defines new low-voltage  ...  Therefore, buses can't support a large number of processors, especially not fast ones.  ... 
doi:10.1109/40.124376 fatcat:3a4opujvrvdllm3aag3cgo6o6a

First- and second-level packaging of the z990 processor cage

T.-M. Winkel, W. D. Becker, H. Harrer, H. Pross, D. Kaller, B. Garben, B. J. Chamberlin, S. A. Kuppinger
2004 IBM Journal of Research and Development  
The processor frequencies are increased to 1.2 GHz, with a 0.6-GHz nest with synchronous double-data-rate interchip and interblade communication.  ...  Each blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve  ...  Acknowledgment The authors would like to thank Roland Frech for performing the VHDM connector measurements and for providing the coupling data in Table 4 .  ... 
doi:10.1147/rd.483.0379 fatcat:hr27o73sjjas7ii7km6q3suk7m

QsNetII: Defining High-Performance Network Design

J. Beecroft, D. Addison, D. Hewson, M. McLaren, D. Roweth, F. Petrini, J. Nieplocha
2005 IEEE Micro  
Scientific codes often use nonblocking communication, and ideally the network and the network interface can make progress with as little processor overhead as possible.  ...  On the one hand, this component interfaces with standard I/O buses, such as peripheral component interconnect (PCI), its extended version (PCI-X), and PCI-Express, thus leveraging commodity computing nodes  ...  Figure 4 shows the Elite4's layout, and Figure 5 shows the optical interface with a 16way switch.  ... 
doi:10.1109/mm.2005.75 fatcat:3bl7i55zfrb5jhjpsahy7564ae

High-Performance Energy-Efficient Multicore Embedded Computing

A. Munir, S. Ranka, A. Gordon-Ross
2012 IEEE Transactions on Parallel and Distributed Systems  
With Moore's law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multicore to exploit this high-transistor density for high performance.  ...  We also discuss modern multicore processors that leverage these HPEEC techniques to deliver high performance per watt.  ...  ACKNOWLEDGMENTS This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC) and the US National Science Foundation (NSF) (CNS-0953447 and CNS-0905308).  ... 
doi:10.1109/tpds.2011.214 fatcat:vagqmojdsjevvc2u2ewqrcjjpq

High-speed interconnect and packaging design of the IBM System z9 processor cage

H. Harrer, D. M. Dreps, T.-M. Winkel, W. Scholz, B. G. Truong, A. Huber, T. Zhou, K. L. Christian, G. F. Goth
2007 IBM Journal of Research and Development  
High frequencies and massively parallel connectivity lead to a raw packaging bandwidth of up to 1,764 GB/s between processors and cache within a single frame for a fully configured four-node z9 system.  ...  speed on all high-speed buses.  ...  Because they are source-synchronous, z9 high-speed interfaces required a sampling clock to be sent along with data. For the z9 off-MCM buses, this meant a differential clock for each data group.  ... 
doi:10.1147/rd.511.0037 fatcat:o6cvkk75rbfebbfiznd2s7cp7m
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