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A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer

Y. MURACHI, J. MIYAKOSHI, M. HAMAMOTO, T. IINUMA, T. ISHIHARA, F. YIN, J. LEE, H. KAWAGUCHI, M. YOSHIMOTO
2008 IEICE transactions on electronics  
We describe a sub 100-mW H.264 MP@L4.1 integerpel motion estimation processor core for low power video encoder.  ...  The proposed processor features a novel hierarchical algorithm, reconfigurable ring-connected systolic array architecture and segmentation-free, rectangle-access search window buffer.  ...  Tetsuya Kamino and Mr. Kosuke Mizuno for their design efforts.  ... 
doi:10.1093/ietele/e91-c.4.465 fatcat:xyya3u72xffs5fwlj3hv4xl5na

A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding

Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008 2008 IEEE International Symposium on Circuits and Systems  
This paper describes a sub 100-mW H.264/AVC MP@L4.1 integer-pel motion estimation processor core for a low power video encoder.  ...  The proposed processor core features a novel hierarchical algorithm, a reconfigurable ring-connected systolic array architecture, and a segmentationfree rectangle-access search window buffer.  ...  We designed a sub 100-mW H.264/AVC main profile motion estimation processor core for MBAFF encoding. 16 × 16, 16 × 8, 8 × 16, and 8 × 8 block sizes are supported for an HDTV resolution video (1920 × 1080  ... 
doi:10.1109/iscas.2008.4541551 dblp:conf/iscas/MurachiMMHIIYLKKY08 fatcat:amjzntjg6vhqzigrknv7z32hea